Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[DisEnchantment]

Well, it is not June yet, and AMD AM5 socket jumped from being behind Intel, to nearly 3x Intel. And it nearly tied AM4.

The x3d is taking the PC gaming by storm:
#1 7800x3d 1860
#2 5800x3d 1070

https://twitter.com/x/status/1645055506275262464

What's interesting to me here is that 3D V Cache 5800 X3D is quite plentiful. And cheap, hovering around the 300 bucks mark in some stores.
I know TSMC has a new fully automated Packaging facility in Chunan inaugurated just 2Qs ago.
But does it mean that they have reached a tipping point to scale packaging for SoIC to cater to a mainstream product?

On the other hand, faster GMI speeds and LLC will negate 3D V Cache benefits for gaming in the future. Unless the Next Gen Cores are bringing a lot more uplift than the tradition we are used to. Then MR DIMMs on the horizon.
Interesting times ahead.

 

[A///]

Unless the Next Gen Cores are bringing a lot more uplift than the tradition we are used to.

Zen 5 should bring that major bump. It's why I myself am hesitant purchasing into Zen 4. Intel won't catch their break for at least another 2 generations, but they release a yearly product. With some exclusions of course.

We have some interesting times ahead of us as you point out. I'm not sure if anyone's wallet is jumping for joy yet.

 

[moinmoin]

I know TSMC has a new fully automated Packaging facility in Chunan inaugurated just 2Qs ago.
But does it mean that they have reached a tipping point to scale packaging for SoIC to cater to a mainstream product?

Whenever I see how much V Cache can improve power consumption I think it must be a perfect fit for Dragon Range in laptops. The fact that V Cache is not being offered there yet tells me that while improving quantity is as of now still too little to expand beyond server and DIY desktop.

 

[uzzi38]

Zen5 (#Turin):
CPP=45nm
M2=30nm
SRAM Target = ~6 GHz at 1.2V
3nm [Zen5 was stamped in and greenlit before N3E was ever announced.]

Zen5c (#Turin-Dense):
CPP=49nm
M2=35nm
SRAM Target = ~5 GHz at 1.2V
4nm [Zen2 -> Zen3, but, Zen4c -> Zen5c // Similar architecture setup]

[Zen5] is only on 3nm. Zen5 in Turin = 3nm, Zen5 in Granite = 3nm, Zen5 in Strix = 3nm.

Someone else has probably pointed this out by now but this is 100% wrong right now, sorry.

Maybe Zen 5 was originally destined to be on N3, but that would have been plans from 1.5+ years ago.

 

[Joe NYC]

What's interesting to me here is that 3D V Cache 5800 X3D is quite plentiful. And cheap, hovering around the 300 bucks mark in some stores.
I know TSMC has a new fully automated Packaging facility in Chunan inaugurated just 2Qs ago.
But does it mean that they have reached a tipping point to scale packaging for SoIC to cater to a mainstream product?

On the other hand, faster GMI speeds and LLC will negate 3D V Cache benefits for gaming in the future. Unless the Next Gen Cores are bringing a lot more uplift than the tradition we are used to. Then MR DIMMs on the horizon.
Interesting times ahead.

If I am not mistaken, that packaging facility is very large - massive.

It's unclear of how much equipment has been put in place, or if it needs a newly designed equipment. I skipped last 2 quarterly calls of TSMC, maybe I will check out the transcripts if there is any news on it.

It seems to me that Hybrid Bond packaging is a gateway to the new phase of chip fabrication so it is strategic area for TSMC. There was a tidbit from Digitimes that NVidia is also looking at SoIC. It seems there is no way around it, considering that the reticle limit for the future process technology nodes will be smaller, so gigantic monolithic chips are not going to be feasible.

I have a feeling that the volume and costs are at the point when this technology is ready for mainstream. I think AMD is going to sell a lot of these, and there will be an iteration of Dragon Range notebook with V-Cache.

Also, since AMD already started putting V-Cache on 6 core chiplets, before too long, we will see 7600x3d, and at that point, we can definitely say that we are reaching mainstream.

I can see that the 7600x3d will reach the current MicroCenter price of 5800x3d, which sells for $299. And it is possible that in H2, AMD may be reaching 50% of the Raphael chips having V-Cache.

So I think the technology may be ready for mainstream implementation, but it seems that Zen 5 may have gone with conservative approach for the server. If MLID slide with arrangement of chiplets is correct.

As far as MRDIMM, I am not sure if they will improve the latency or only bandwidth. It seems that there will be 2 banks running at half speed feeding the interface. Even at full speed, it is not close to SRAM latency.

 

[CakeMonster]

Ian on reddit:

Regarding the graphs. I saw some really crappy reporting on it. Zen 5 is well after Jim left, and besides, he doesn't consider himself the father of Zen (see my first interview with Jim). He sees himself the crazy uncle. It's Mike Clark who considers himself the father of Zen (see my interview with Mike), and he stated that they were working on Zen 5 during the Zen+/Zen2 era, after Jim had left. Zen5 is a ground-up blank page design, not an optimization, so it'd be a gen beyond what Jim was working on (and Jim was focusing more on the Arm design more anyway). Jim's numbers on Zen 5 were purely projected/estimated, based on Zen 4 numbers, and Jim's confidence in the team. They failed to put that as a disclaimer on the graph - the focal point of the graph was meant to be the Ascalon performance comparison, not the Zen 5 estimate.

 

[nicalandia]

Jim from Adore TV appears to have access to Turin Cinebench R23 scores




Without any tweaking 2S 9654 Genoa are as fast as 1P 9654 Genoa on Cinebench R23.

 

[Geddagod]

Jim from Adore TV appears to have access to Turin Cinebench R23 scores

View attachment 79368


Without any tweaking 2S 9654 Genoa are as fast as 1P 9654 Genoa on Cinebench R23.

So does Tom it looks like

 

[Asterox]

So does Tom it looks like
View attachment 79369

More details, L1 Cache per core is bigger on Zen 5.

 

[nicalandia]

So does Tom it looks like
View attachment 79369

So 123,000 points on 128 Cores? Thats really underperforming, but its a ES so its expected

 

[Markfw]

So 123,000 points on 128 Cores? Thats really underperforming, but its a ES so its expected

It beats Genoa at the same core count, so why is it disappointing ?

 

[nicalandia]

It beats Genoa at the same core count, so why is it disappointing ?

96 Core Genoa is making over 110,000 poits Zen3 EPYC gets over 113,000 points. So its not that impressive but as I mentioned, its an ES




By the Way, Stock Sapphire Rapids 2S Cant even break the 100,000 poits mark that was beat by stock Zen2 Ages ago

 

[DisEnchantment]

96 Core Genoa is making over 110,000 poits and Zen2 with 128 cores(2S) get 101,000 points. So its not that impressive but as I mentioned, its an ES.

Zen 5 in shambles, 128C Genoa > 128C Turin in CBR23. Bulldozer here we come

Good ole Tom leaked ChatGPT generated image.

 

[nicalandia]

Zen 5 in shambles, 128C Genoa > 128C Turin in CBR23. Bulldozer here we come

Not really, its an ES sample and to this date Sapphire Rapids can't break the 100,000 points Barrier Zen2 EPYC CPU broke long ago so Rome >>Sapphire Rapids?

 

[Geddagod]

Not really, its an ES sample and to this date Sapphire Rapids can't break the 100,000 points Barrier Zen2 EPYC CPU broke long ago so Rome >>Sapphire Rapids?

I think he was joking haha
But anyway, L1 cache changes are interesting. 80KB sounds similar to the cache set up Intel has, maybe Zen 5 also does 32KB instruction + 48KB data L1 caches?

 

[BorisTheBlade82]

As he mentioned in the video as well and was also already posted by @nicalandia : There are some real challenges regarding Windows and CBR23 when benchmarking such high thread count systems.

So it's rather difficult to take the CB scores of >64 thread systems under Windows non-Enterprise at face value.

When including that factor, the score looks pretty solid for an ES - although it still might be totally made up.

 

[nicalandia]

As he mentioned in the video as well and was also already posted by @nicalandia : There are some real challenges regarding Windows and CBR23 when benchmarking such high thread count systems.

So it's rather difficult to take the CB scores of >64 thread systems under Windows non-Enterprise at face value.

When including that factor, the score looks pretty solid for an ES - although it still might be totally made up.

I believe thats what we may be seeing here an actual 128 Core CPU but being split in two by Windows 10, like this Threadripper 3990X







If thats the case, then the Performance should be Higher with the correct OS, testing these massive CPUs with Linux is just much better. It would be interesting to see what is the Cinebench R23 under Clear Linux and Wine.

 

[yuri69]

Regarding the results, the YT slide states it's not a single 128c CPU but 2 sockets of 64c CPUs (each consisting of 8 * 8c CCD).

 

[A///]

Those two? those two got access to es hardware before reputable news sites like anandtech? what is going on... Like giving a goat access to a warehouse of fancy cashmere sweaters.

 

[BorisTheBlade82]

Those two? those two got access to es hardware before reputable news sites like anandtech? what is going on... Like giving a goat access to a warehouse of fancy cashmere sweaters.

That, sadly, is the state, that Tech Journo is in.
Not to say that it is all their fault. People not wanting to pay for valuable content and not even being okay with disabling their ad-blockers are the root cause IMHO. </OT>

 

[A///]

That, sadly, is the state, that Tech Journo is in.
Not to say that it is all their fault. People not wanting to pay for valuable content and not even being okay with disabling their ad-blockers are the root cause IMHO. </OT>

why not give samples to the guy who makes 2 hour long videos and has hair reaching the ground?

 

[DisEnchantment]

As he mentioned in the video as well and was also already posted by @nicalandia : There are some real challenges regarding Windows and CBR23 when benchmarking such high thread count systems.

So it's rather difficult to take the CB scores of >64 thread systems under Windows non-Enterprise at face value.

When including that factor, the score looks pretty solid for an ES - although it still might be totally made up.

The problem is not the benchmark itself, the problem is where it originated from. I have to admit I might be a bit too critical of these few folks.
But had it been someone else like Execufix for instance, I would be more willing to ponder more about it. But I am also aware about CB R23/ Windows behavior in this high thread count scenario.

 

[Gideon]

The problem is not the benchmark itself, the problem is where it originated from. I have to admit I might be a bit too critical of these few folks.
But had it been someone else like Execufix for instance, I would be more willing to ponder more about it. But I am also aware about CB R23/ Windows behavior in this high thread count scenario.

I don't think you are too critical at all. MLID is an absolute incomprehensible clown. I have no idea how people still take him seriously.

A ton of his "leaks" were just again proven fundamentally wrong (and no they are not excusable by their usual "change of plans" card).

The majority of his leaks constantly ignore basic fundamentals of the industry (changes to silicon, months prior to release, prices known a year before release, etc ...).
And the ones that do not, often seem just super-obvious speculation. Either by himself or by his "sources", that he is either parroting uselessly or for clicks.

Just one relatively recent example:

How is he still constantly getting resonance and validation every time a new 20 minute video goes up is totally beyond me.

Just bookmark these screenshots above and, especially the Turin-dense CCX part (*sigh* "dense" indeed) and take a look at these once Zen 5 is actually released.

But I'm sure it's all 100% accurate and AMD just "decided to change cache sizes last minute" when it eventually doesn't match reality.

 

[DisEnchantment]

Ian on reddit:

Regarding the graphs. I saw some really crappy reporting on it. Zen 5 is well after Jim left, and besides, he doesn't consider himself the father of Zen (see my first interview with Jim). He sees himself the crazy uncle. It's Mike Clark who considers himself the father of Zen (see my interview with Mike), and he stated that they were working on Zen 5 during the Zen+/Zen2 era, after Jim had left. Zen5 is a ground-up blank page design, not an optimization, so it'd be a gen beyond what Jim was working on (and Jim was focusing more on the Arm design more anyway). Jim's numbers on Zen 5 were purely projected/estimated, based on Zen 4 numbers, and Jim's confidence in the team. They failed to put that as a disclaimer on the graph - the focal point of the graph was meant to be the Ascalon performance comparison, not the Zen 5 estimate.

Tenstorrent YT video is no longer available. Not only that slide shoddily put together, even if they have access to real data they should not have put it the way they did.

 

[A///]

there's more chin to mlid than brains. i wish this forum censored anything related to him.