Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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PJVol

Senior member
May 25, 2020
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That s not much difficult to spot what went wrong with RDNA3, the chips still clock quite high but methink that for some reasons there were some critical circuitries within the GPU that didnt clock accordingly with the projected stock voltage.
This could have been fixed by the respin if occured, unless there was a flaw at DTA/STA.
And while I generally agree that the clocks seem okay, there can be several causes.

I'd say an occupancy issue on the GCD side hampering performance scaling, plus the off-die cache / logic / interconnect subsystem came out quite the power-hog.
The former is probably fixed in rdna 3.5-4, and got rid of the latter until it's ready. Both can't be fixed just upon respin
 
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uzzi38

Platinum Member
Oct 16, 2019
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That s not much difficult to spot what went wrong with RDNA3, the chips still clock quite high but methink that for some reasons there were some critical circuitries within the GPU that didnt clock accordingly with the projected stock voltage.

It can be only 10% of the whole chip but they had to increase voltage by about 10%
for the whole to get the flawed parts working with inconditional stability, and at this rate this did increase the comsumption by 20% wich led to the missed perf/watt target, guess that it should be the main fix that will be done with RDNA3.5.
Well we don't have to wait long to get some actual potential proof, Strix and Strix Halo should put to rest whether or not there was an actual issue with RDNA3 soon enough.
 

StefanR5R

Elite Member
Dec 10, 2016
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Anyhow, Apple clocking their cores higher is needed to compete in desktop. This is where AMD and Intel have huge lead.
Why does it matter? If Apple is able to have higher IPC than AMD/Intel, it makes up for the clock speed disadvantage.
This is not how (or with whom) Apple competes. They are a systems seller and a software and service provider.

Currently, Apple are content with putting laptop chips into their range of desktop computers. IIRC, they have also been content at some point in the past to put an OS without NUMA capability onto their then existing range of dual-socket computers, for example. Though everything has technical limits eventually, e.g. they switched to Intel after the PowerPC maker(s) abandoned the mobile sector.

Reaching Apple's IPC level does not guarantee reaching Apple's efficiency level.
The first bunch of Zen 5 based products will be MCMs with 4nm chips. So there is that.
Would be interesting if folks made measurements once Zen 5 based mobile devices are out. (In the past, there has been lots of idle talk at a level of benchmark-score-divided-by-power-limit, and disappointingly little in the way of actual measurements.)
 

yuri69

Senior member
Jul 16, 2013
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This could have been fixed by the respin if occured, unless there was a flaw at DTA/STA.
And while I generally agree that the clocks seem okay, there can be several causes.

I'd say an occupancy issue on the GCD side hampering performance scaling, plus the off-die cache / logic / interconnect subsystem came out quite the power-hog.
The former is probably fixed in rdna 3.5-4, and got rid of the latter until it's ready. Both can't be fixed just upon respin
RDNA3 timeline:
* the ultimate nVidia-beater - Navi 31 - 15k shaders => over 90TFLOPS!
* still utter devastation - Navi 31 - 12288 shaders is over 2x of Navi 21's 5120!
* wait for the RX7900 respin - Navi 31 is broken - revision A0, lol!
* no respin, but RDNA3 is fixed in later designs like Navi 32!
---
* the fix is what RDNA3.5 is about!
* these were APUs... wait for RDNA4!
* these got no highend... wait for RDNA5!
 

Ghostsonplanets

Senior member
Mar 1, 2024
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This is the Z5 thread, but if we are to talk about RDNA 3, Xino shared that STX 12 CU (Full implementation is 16 CU) 22 - 24W scores ~3150 TS.

Phoenix was around 2400? At the same wattage.

So that's a nice boost. Maybe the power scaling and clocking issues are fixed on RDNA 3.5, alongside the backported sALU.
 
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FlameTail

Platinum Member
Dec 15, 2021
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Imagine a Strix Halo laptop with 256 GB RAM (made possible thanks to the 256 bit bus).

50 TOPS NPU + 273 GB/s + 32 MB IC + 256 GB RAM

Run 200+ GB AI models on-device!
 

Glo.

Diamond Member
Apr 25, 2015
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This is the Z5 thread, but if we are to talk about RDNA 3, Xino shared that STX 12 CU (Full implementation is 16 CU) 22 - 24W scores ~3150 TS.

Phoenix was around 2400? At the same wattage.

So that's a nice boost. Maybe the power scaling and clocking issues are fixed on RDNA 3.5, alongside the backported sALU.
So full Strix Point should be around 4k points in TS. Thats RX 6400 desktop territory, without its VRAM capacity limitations.
 

Ghostsonplanets

Senior member
Mar 1, 2024
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So full Strix Point should be around 4k points in TS. Thats RX 6400 desktop territory, without its VRAM capacity limitations.
For such a cache/bandwidth starved implementation of RDNA, that's really good. AMD basically giving an integrated RTX 3050 35 - 50W with every STX SoC, but without the VRAM bottleneck.

In theory, OEMs could create T&L entry level Gaming Laptops with it. Or users could simply buy an office/premium T&L laptop and still be able to game at 1080p Low/Medium with reasonable settings.
 

Hitman928

Diamond Member
Apr 15, 2012
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Apple does not have higher IPC than Intel or AMD. They do have the best TSMC silicon but that's it.

Apple's CPUs have significantly higher IPC than anything Intel or AMD at this moment. Even if you take the M1 on TSMC 5 and compare to AMD and Intel's best on TSMC 5 or Intel 4, the Apple CPUs have a large IPC advantage. Their IPC advantage comes down to architecture and has nothing to do with the node used when compared to AMD's and Intel's latest.