I expect a monolithic 7nm die.
That doesn't really make much sense.
The reason AMD went with the chiplet design in the first place is to reduce cost.
It allows AMD to move the I/O to a separate 14nm die, making the 7nm die smaller and cheaper.
Now, AMD is going to put the cores + I/O + iGPU on a single 7nm die?
That would be expensive.
Monolithic designs work better for mobile PCs, which is the market AMD really needs to penetrate. If they went with a chiplet design, it'd require three dies on-package (CPU, iGPU+I/O, and Southbridge), as opposed to just two (CPU and Southbridge) on Intel's mobile chips.That doesn't really make much sense.
The reason AMD went with the chiplet design in the first place is to reduce cost.
It allows AMD to move the I/O to a separate 14nm die, making the 7nm die smaller and cheaper.
Now, AMD is going to put the cores + I/O + iGPU on a single 7nm die?
That would be expensive.
AMD did confirm long ago that Renoir is monolithic design.
Renoir is monolithic as far as anyone knows. Multiple people asked if it was "Matisse'd" which AMD said "no u".
Zen2/VCN2/GCN-Vega2.0/etc all on one die = Renoir
There is potential for extra details like Renoir being on N7P(N7 plus on DUV). Utilizing the mobile libraries which are 6-track, rather than the 7.5-track on Matisse/Vega20.
It's cost is dependent on core and CU amounts, we have no idea so far what those are, but my bet would be 4-6 CPU cores (6 is an unlikely maybe) and 20 CU.I don't think a monolithic APU on 7nm will be that expensive. It's a fairly mature node now. I bet the die size is well below 200mm^2.
It's cost is dependent on core and CU amounts, we have no idea so far what those are, but my bet would be 4-6 CPU cores (6 is an unlikely maybe) and 20 CU.
That should be smaller, there is no way they put 32MB of L3 in there, even 16MB is highly unlikely, 8MB is most probable and that cuts the die size by more than a third.Given the size of a Z2 CCX die (71 mm2)
The reason AMD went with the chiplet design in the first place is to reduce cost.
Vega instead of NAVI is all but confirmedIm going for 4C 8T + 10CU Navi monolithic die (140mm2 ??)
If it is Vega based then meh.
That should be smaller, there is no way they put 32MB of L3 in there, even 16MB is highly unlikely, 8MB is most probable and that cuts the die size by more than a third.
IT will most probably be monolithic. Power management in very-low-power environments requires at least an interposer, if they do it with chiplets (just look at Zen2 idle low-usage temp/power numbers) . The Desktop/Server design just wouldn't cut it.
The main purpose of the chiplets was to scale from 6-8core desktop chips all the way to server. These devices are pretty similar in that they don't run on batteries. Mobile APUs are a bit different story. I can imagine AMD moving to chiplets eventually, but the packaging needs to change considerably before that. At least an interposer, or something more similar to Intel FOREVOS.
If it is Vega based then meh.
AMD made the financial commitments necessary to produce Raven Ridge and Picasso. Those both differed from Summit Ridge and Pinnacle Ridge in die layout. It's really no different with Renoir. Also, I do not think AMD wants to implement the Renoir iGPU in GF 12nm either (which would be necessary were they to integrate the iGPU into the I/O die).