Zen 2 APUs/"Renoir" discussion thread

[TheRookie]

What do you expect from Zen 2 APUs/"Renoir"?

 

[TheRookie]

I would guess that Renoir is like Matisse except with the iGPU on the I/O die.

 

[NTMBK]

I expect a monolithic 7nm die.

 

[TheRookie]

I expect a monolithic 7nm die.

That doesn't really make much sense.

The reason AMD went with the chiplet design in the first place is to reduce cost.

It allows AMD to move the I/O to a separate 14nm die, making the 7nm die smaller and cheaper.

Now, AMD is going to put the cores + I/O + iGPU on a single 7nm die?

That would be expensive.

 

[naukkis]

AMD did confirm long ago that Renoir is monolithic design.

 

[burninatortech4]

That doesn't really make much sense.

The reason AMD went with the chiplet design in the first place is to reduce cost.

It allows AMD to move the I/O to a separate 14nm die, making the 7nm die smaller and cheaper.

Now, AMD is going to put the cores + I/O + iGPU on a single 7nm die?

That would be expensive.

I don't think a monolithic APU on 7nm will be that expensive. It's a fairly mature node now. I bet the die size is well below 200mm^2.

 

[Gideon]

Linux software taking shape

https://www.phoronix.com/scan.php?page=news_item&px=AMD-Renoir-APU-Gfx-Power-Man

 

[BigDaveX]

That doesn't really make much sense.

The reason AMD went with the chiplet design in the first place is to reduce cost.

It allows AMD to move the I/O to a separate 14nm die, making the 7nm die smaller and cheaper.

Now, AMD is going to put the cores + I/O + iGPU on a single 7nm die?

That would be expensive.

Monolithic designs work better for mobile PCs, which is the market AMD really needs to penetrate. If they went with a chiplet design, it'd require three dies on-package (CPU, iGPU+I/O, and Southbridge), as opposed to just two (CPU and Southbridge) on Intel's mobile chips.

 

[TheRookie]

AMD did confirm long ago that Renoir is monolithic design.

source?

 

[NostaSeronx]

Renoir is monolithic as far as anyone knows. Multiple people asked if it was "Matisse'd" which AMD said "no u".

Zen2/VCN2/GCN-Vega2.0/etc all on one die = Renoir

There is potential for extra details like Renoir being on N7P(N7 plus on DUV). Utilizing the mobile libraries which are 6-track, rather than the 7.5-track on Matisse/Vega20.

 

[TheRookie]

Renoir is monolithic as far as anyone knows. Multiple people asked if it was "Matisse'd" which AMD said "no u".

Zen2/VCN2/GCN-Vega2.0/etc all on one die = Renoir

There is potential for extra details like Renoir being on N7P(N7 plus on DUV). Utilizing the mobile libraries which are 6-track, rather than the 7.5-track on Matisse/Vega20.

"as far as anyone knows" doesn't mean anything

As far as anyone know, the Loch ness Monster exists.

 

[soresu]

I don't think a monolithic APU on 7nm will be that expensive. It's a fairly mature node now. I bet the die size is well below 200mm^2.

It's cost is dependent on core and CU amounts, we have no idea so far what those are, but my bet would be 4-6 CPU cores (6 is an unlikely maybe) and 20 CU.

 

[TheRookie]

It's cost is dependent on core and CU amounts, we have no idea so far what those are, but my bet would be 4-6 CPU cores (6 is an unlikely maybe) and 20 CU.

Well, each CCX has 4 cores.

So, if there there are 6 cores SKUs, there will certainly be 8 cores SKUs.

It also make sense for AMD to release 8 cores SKUs because Intel also has 8 cores mobile processors.

Also, having a lot of CU don't make sense when the when the bottleneck is the memory bandwidth.

 

[soresu]

Given the size of a Z2 CCX die (71 mm2) + Vega 7nm at 20CU (336 mm2 x 0.3125 = 105 mm2) = 176 mm2.

Of course that is a very rough estimate given V20 has 4 HBM stack IO's, and the CCX die has nothing but IF links for IO.

I would put the total number closer to 180-190 mm2.

 

[amd6502]

Does 20CU really make sense for mobile? I was thinking more along 8 to 11.

If they shoot for ultra low power 10W tdp then it should be monolithic.

I still see there would be a possible fleeting/temporary APU generation that isn't ULP focused; this becomes likelier if Zen3 is close to ready. In this case, make Zen2 APU a low cost MCM project based on existing chiplet, with it being focused primarily on desktop and OEM. Then mobile focused Zen3 follows close behind, optimistically with a midyear '20 launch.

Picasso won't give them leadership in mobile, but it is pretty good.

If Renoir were MCM, i think there would still be mobile derivatives. Even 15W might still well be possible with 8c MCM. Igpu gaming would be out of the question, but if gpu is idle or unused (as in dgpu gaming laptops) the chiplet could still have a nice boost freq. The base freq would be on low side, but likely acceptable.

 

[Gideon]

Given the size of a Z2 CCX die (71 mm2)

That should be smaller, there is no way they put 32MB of L3 in there, even 16MB is highly unlikely, 8MB is most probable and that cuts the die size by more than a third.

IT will most probably be monolithic. Power management in very-low-power environments requires at least an interposer, if they do it with chiplets (just look at Zen2 idle low-usage temp/power numbers) . The Desktop/Server design just wouldn't cut it.

The main purpose of the chiplets was to scale from 6-8core desktop chips all the way to server. These devices are pretty similar in that they don't run on batteries. Mobile APUs are a bit different story. I can imagine AMD moving to chiplets eventually, but the packaging needs to change considerably before that. At least an interposer, or something more similar to Intel FOREVOS.

 

[DrMrLordX]

The reason AMD went with the chiplet design in the first place is to reduce cost.

AMD made the financial commitments necessary to produce Raven Ridge and Picasso. Those both differed from Summit Ridge and Pinnacle Ridge in die layout. It's really no different with Renoir. Also, I do not think AMD wants to implement the Renoir iGPU in GF 12nm either (which would be necessary were they to integrate the iGPU into the I/O die).

 

[AtenRa]

Im going for 4C 8T + 10CU Navi monolithic die (140mm2 ??)

 

[Gideon]

Im going for 4C 8T + 10CU Navi monolithic die (140mm2 ??)

Vega instead of NAVI is all but confirmed

My guess is that the top-of-the-line chip is 8C 16T with 8MB L3.

There will be at least one 8C model with 25W and perhaps even one with 15W, though the latter will most probably max out @ 6 Cores.

I'm unsure about the number of CUs. If they don't use LPDDR4 (which i really hope it does) it doesn't matter much any way, as it will be terribly bandwidth bound

 

[AtenRa]

If it is Vega based then meh.

 

[NostaSeronx]

If Renoir was chiplet, it would probably be close to this;
https://img.techpowerup.org/190827/renoirchiplet.png
&

http://imgur.com/Mu9SGZS

With Dali abandoning the second IF link and using 12FDX/22FDX for the I/O die. (2 cores in the complex + 8 CUs in the GPU complex)
Where Renoir(or successors) would be capable of 2x CCX(2x Quad-core) and 2x Shader Engines(>12 CUs and up), etc.

Monolithic for reduced compute data movement. It needs to be coherent(via AMD spec) within the die for most heterogeneous compute operations. There is always room for VCN-Next which runs CPU+GPU+VCN for encoding at extremely high quality.

 

[dainthomas]

If it is Vega based then meh.

I was skipping the 3400g in anticipation of the next APU having Navi. Dammit.

 

[eek2121]

That should be smaller, there is no way they put 32MB of L3 in there, even 16MB is highly unlikely, 8MB is most probable and that cuts the die size by more than a third.

IT will most probably be monolithic. Power management in very-low-power environments requires at least an interposer, if they do it with chiplets (just look at Zen2 idle low-usage temp/power numbers) . The Desktop/Server design just wouldn't cut it.

The main purpose of the chiplets was to scale from 6-8core desktop chips all the way to server. These devices are pretty similar in that they don't run on batteries. Mobile APUs are a bit different story. I can imagine AMD moving to chiplets eventually, but the packaging needs to change considerably before that. At least an interposer, or something more similar to Intel FOREVOS.

32 mb L3 cache wouldn’t be a problem. Look at how small Zen 2 dies are. You have to realize we are looking at a smaller node. While there are tons of rumors out there, I am placing bets on a regular Zen 2 design with a reworked boost algorithm and lower clocks. The Ryzen 5 3600 is a 65watt chip, so it’s hardly a stretch to lower the clock speeds for power savings and add an APU.

 

[eek2121]

If it is Vega based then meh.

There is nothing wrong with Vega. At lower clocks it sips power. The reason why it used so much power on the desktop is due to it being outside the efficiency curve.

 

[jpiniero]

AMD made the financial commitments necessary to produce Raven Ridge and Picasso. Those both differed from Summit Ridge and Pinnacle Ridge in die layout. It's really no different with Renoir. Also, I do not think AMD wants to implement the Renoir iGPU in GF 12nm either (which would be necessary were they to integrate the iGPU into the I/O die).

With the setup AMD has right now, the IGP needs to be on the same die as the memory controller. So they could make a new IO die on TSMC 7 nm and use that. I agree that they are more likely to do monolithic.

I still think there's a chance they put a GDDR6 controller, although obviously that would only be on mobile.