That's a good point . Steamroller is going to have some design choices which are shared with Jaguar family. They are implemented as both performance and power improving techniques( dynamically shared re-sizeable L2 cache with multiple banks that can clock up/down to preserve power and/or improve single threaded execution performance).Maybe one of the reasons to prefer 28nm bulk over 32nm SOI could be the ability to share larger parts of the design with the "Cat" family? E.g. the banked dynamic L2 cache that seems to be eerily similar in Jaguar and Steamroller ?
the static and dynamic leakage value ought to markedly increase with the 28nm non-SOI process over that which AMD is already relying on with the existing 32nm SOI process.
the chips themselves would not be expected to perform any better (nor worse) than today's chips in terms of clockspeeds and power consumption - but there is the opportunity for IPC improvements of course.
Unlikely since they maintain high frequency as a design feature
while pointing higher efficency for next node iterations.
http://technewspedia.com/the-new-micro-architecture-modular-amd-steamroller/
AMD's Steamroller Detailed: 3rd Generation Bulldozer Core
The tradeoff is peak frequency. These heavily automated designs wont be able to clock as high as the older hand drawn designs.
AMD believes the sacrifice is worth it however because in power constrained environments (e.g. a notebook) you wont hit max frequency regardless, and youll instead see a 15 - 30% energy reduction per operation. AMD equates this with the power savings youd get from a full process node improvement.
We wont see these new libraries and automated designs in Steamroller, but rather its successor in 2014: Excavator.
@IDC
I don't know how 28nm will end up but their 32nm SOI is definitely not what AMD had in mind for Bulldozer. Leakage is pretty bad, yields are subpar to 45nm and cost is probably more than what AMD was expecting. 28nm needs to be seriously screwed up in order to be worse than this process node they are on now.
Bulk is no cheaper than SOI past 32-nm do to physicality.And to be sure, even if it is no better clockspeed or leakage wise, the production costs per chip will be markedly lower because (1) no SOI wafer cost, and (2) higher xtor density means more chips per wafer.
6800K running at 3.2Ghz? Even if it had 35W TDP it would be called a failure in reviews, sorry. No magic pixie dust can bridge 18+% clock deficit. They need faster x86 core in 2013, not slower.A10-5800K 3.8 GHz @ ~1.4 volts <-- 32-nm SHP
A10-6800K 3.2 GHz @ ~1.1-1.2 volts <-- 28-nm LPH
5.2 GHz @ 1.55 volts6800K running at 3.2Ghz? Even if it had 35W TDP it would be called a failure in reviews, sorry. No magic pixie dust can bridge 18+% clock deficit. They need faster x86 core in 2013, not slower.
Yeah and you typed it on your invisible keyboard I guess?5.2 GHz @ 1.55 volts
You happy now? .
The issue with that is that there is no VLIW4 GPUs to crossfire within the 8000 series. All of the 8000 series use Graphic Core Next 2.0 clusters.6800K can actually be option number 1 or 2 in the poll,same 32nm PD based core,similar CPU clock or a small bump(4Ghz instead of 3.8Ghz? not that it will make much difference) and a bit better GPU.
Yeah the hybrid CFX was one of important selling points AMD used before. This brings us to following dilemma:The issue with that is that there is no VLIW4 GPUs to crossfire with in the 8000 series. All of the 8000 series use Graphic Core Next 2.0 clusters.
pcquest said:AMD provided an early look at its new 2013 accelerated processing units (APU) and announced a new OEM relationship with VIZIO. At an International Consumer Electronics Show (CES) event for press and analysts, AMD demonstrated working silicon of its first system on chip (SoC) APUs, “Kabini” and “Temash”, both scheduled to ship in the first half of 2013. Demonstrations included a range of leading-edge applications and games on a “Kabini”-based ultrathin notebook and a “Temash”-based performance tablet and hybrid notebook.
AMD also introduced the new “Richland” APU, which is currently shipping to OEMs, which delivers a 40 percent increase in performance over the previous generation of A-Series APUs. “Richland” is expected to come bundled with new software for consumers such as gesture and facial recognition to dramatically expand and enhance consumers’ user experiences. The follow-on to “Richland” will be the 28nm “Kaveri” APU with revolutionary heterogeneous system architecture (HSA) features and is expected to begin shipping to customers in the second half of 2013.
Additionally, AMD announced a new series of discrete graphics processors for performance gaming that is already shipping to customers, the AMD Radeon HD 8000m series. These latest products are reflective of the company’s strategy to focus on creating differentiated IP leadership through low-power technologies that target the high-growth client markets such as ultrathin, convertible and tablets.
“With a groundbreaking new APU line-up in 2013, AMD is poised to win in high-growth consumer segments,” said Lisa Su, senior vice president and general manager, AMD Global Business Units. “We are developing technologies with end users in mind – to bring true surround computing and immersive experiences to our everyday lives. It is exciting to bring our leadership APU technologies to market including the industry’s first x86 quad-core SoC, while building on our leadership in graphics and gaming.”
Well its outstanding is what it is only 4 piledriver cores Vs 8 on trinity. Unless AMD is tring to say they only have 4 cores now . It has to hurt. intel 4 cores beat AMDs 8 cores . A 40% increase in performance tho they aren't showing bench marks like intel did with conroy . If AMD was 40% faster than present AMD stuff their would Benchmarks at CES.
It will auto-close in a few days. Good pickPoll can be closed. Piledriver+VLIW4+32nm confirmed by AMD. Yeah my vote was right.
Poll can be closed. Piledriver+VLIW4+32nm confirmed by AMD. Yeah my vote was right.
If you look at the roadmap AMD gave out at CES yesterday, the "delay" of Kaveri seems like a minor bump now. It was always supposed to launch in Q2 or Q3 2013,now we have it as Q4 probably. So the delay is really a quarter or so. It's coming and important thing is that SR core is not "cancelled" like some reported.It's the only option that made sense given how recently it showed up on the roadmaps after SR got delayed. AMD learned from the Brazos 2.0 launch. Even if you don't really have anything new, make it appear all new and shiny anyway. Still, up to 40% more performance (has to be GPU) is very impressive. Some sort of GPU turbo is my guess, combined with higher memory bandwidth, possibly more shaders too.
The technical issue with going "32nm SOI/HKMG -> 28nm bulk/HKMG" is not that Idrive will remain flat or go down (because it won't, Idrive assuredly will go up with 28nm over 32nm) but the static and dynamic leakage value ought to markedly increase with the 28nm non-SOI process over that which AMD is already relying on with the existing 32nm SOI process.
That much must be true unless the existing SOI-implementation in 32nm is so shoddy, so crappy and so un-optimized, that its removal from the process flow results in nary a difference in static or dynamic leakage.
So we must either assume them to be fools for going to the expense of using SOI at 32nm, or assume them to be fools for bothering to pay for taping out chips for 28nm that don't have SOI, because process-technology wise this should result in little more than trading six of one thing for a half dozen of another.
The primary benefit here from such a node transition "32nm SOI/HKMG -> 28nm bulk/HKMG" is AMD and the cost per die. The wafers will certainly yield more dies/wafer because the 28nm xtors will have higher density (smaller die) and without the SOI tax the wafers will only be slightly more expensive than the existing 32nm ones.
So AMD gets to sell chips which cost them much less per chip, but the chips themselves would not be expected to perform any better (nor worse) than today's chips in terms of clockspeeds and power consumption - but there is the opportunity for IPC improvements of course.
(unless 32nm SOI is just so badly borked that 28nm without SOI does actually turn out to still be just that much better...)