I think you are mistaken believing that Sunny Cove is horribly inefficient and is a repeat of Netburst with some magic "Banias" core coming in to replace it, and that'll be Tremont.
I actually think that Sunny Cove is pretty good. 18% IPC over Skylake - if true - would make Intel competitive again, even if it were competing head-to-head with Zen3 (though it would have been better for Intel to pit it against Zen2). The real problem is that Intel has not chosen to release any products featuring Sunny Cove to date that have more than four cores. So yields are bad, clocks are sketchy, etc. etc. And, furthermore, Tremont itself may wind up with similar problems. Intel may not be able to fab dice with more than some unfortunately-low number of Tremont cores on it before suffering such low yields using their 10nm process that they'll have to scratch the entire product.
But then look at Lakefield.
Instead of doing something radical (and potentially useful) like stacking multiple 4c IceLake dice via Foveros (put the I/O die + iGPU in the middle I guess), they chose only one Sunny Cove core and four Tremont cores in a custom die, stacked it with some RAM and an I/O die, and created Lakefield as the "pipecleaner" product for Foveros. Intel is up against the wall here. Their "Netburst" moment of today is that they're relying on high-clockspeed -Lake cores (4 GHz+) operating in numbers as high as 8 or higher all being fabbed on one monolithic die with the memory controller, iGPU, and other SoC functions. For whatever reason, they can't do it on their new 10nm process. What if they can't do it on 7nm either, even if 7nm yields prove to be less-problematic? AMD sidestepped this problem by limiting the number of cores per die to 8 and tying them together with IF. If Intel can't keep the monolithic train rolling, they'll have to do the same thing with their packaging technologies - EMIB and Foveros. But going back to Lakefield . . . Intel isn't even trying to stack Sunny Cove yet, and there does not seem to be any indication that they'll do so in a followup product. We see Rocket Lake - another monolithic design except for probably the iGPU - in 2021. We see Tiger Lake (Willow Cove) in 4c configurations, carrying on as a successor to IceLake. Unless 6c and 8c TigerLake are a thing? I haven't heard about those. We don't see 8c-16c Sunny or Willow Cove products coming up that relying on chip stacking, or anything of the sort, which is what Lakefield
implies that Intel could do, if such a configuration could be made to work at all.
What if such a configuration
can't work, but something involving Tremont can? Due to power density or some other factor I can't imagine at the moment. Tremont alone can't save Intel, but something 3 or 4 steps down the line with the same basic TDP targets and better performance, stacking via Foveros in 16c configurations or better, might start hunting bear for Intel while they struggle to make the Coves make sense. Or, to put it differently: what if Intel's Atom team can develop successors to Tremont that by 2023 or so, are competitive on a clock-per-clock basis with Apple's A-series, use about as much power per core as Apple's A-series, and can be stacked in ridiculous quantity? With clockspeeds maybe in the 3-3.5 GHz range? Also consider that I'm talking about A14 or A15, or wherever Apple will be by 2023. Not just A13 today.
The Coves may be relegated to duty in massive server-class packages where they can EMIB a bunch of 4c Cove-based dice. Sadly we haven't seen Intel try that yet, either.
Or Intel's future may be that the Coves will be relegated to the position of one or two per die, with clusters of Atoms supporting, either on the same die or on dice stacked via Foveros. That still shifts a great deal of Intel's future towards Atom, since overall system performance will still be limited by the performance of Tremont and/or its successors.
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