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The Intel Atom Thread

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IntelUser2000 said:
No one wants to make groundbreaking new designs when they are only in the business of making $1 controller chips for your hard drive or SSD.
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RealTek does! LOL

(Compare Adata SX8200 2TB NVMe PCI-E 3.0 x4 SSD, with Silicon Motion controller for $280, versus SX8100 2TB NVMe with RealTek controller for $200.)
 
VirtualLarry said:
RealTek does! LOL
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Hah! That's very true.

Few years ago I read that Apple only has 25% of the volume share, but 80% of the revenue share. Out of the 20% revenue share left, 80% is taken up by Samsung. So about a dozen Smartphone guys are competing for the 4-5% left over.

If it wasn't for Apple making Smartphones wildly popular ARM may never have advanced this far. But it was inevitable, because the spirit of Moore's Law says you get the same computer in a smaller space and form factor.

I think the free licensing model for the ARM ISA is the reason they adopted it. Had Intel been open with the x86 ISA perhaps it would have been more common. Everything eventually comes back to you. Even the decisions made 20+ years ago.
 
IntelUser2000 said:
I think the free licensing model for the ARM ISA is the reason they adopted it. Had Intel been open with the x86 ISA perhaps it would have been more common. Everything eventually comes back to you. Even the decisions made 20+ years ago.
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I'm sure that you meant "free" as in "without restriction on the particular company" rather than "fee-free", as I'm fairly sure that licensing fees are involved.

Speaking of decisions made 20 years ago... hello Meltdown/Spectre.
 
VirtualLarry said:
I'm sure that you meant "free" as in "without restriction on the particular company" rather than "fee-free", as I'm fairly sure that licensing fees are involved.
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Yes, thank you that's what I mean. I should have said open.

I can even talk about what-ifs with Itanium. Let's say if it took hold. Now we'd have the same problem with Intel unable to scale down, but with EPIC ISA. Maybe even worse because that team was having tremendous difficulty scaling up the performance. At its peak it performed slightly better than Conroe, maybe at Penryn levels.

A company big as Intel needs wake-up calls such as with WoA and also AMD. I'm pretty sure open x86 would have had Nvidia join in.

I do get when our former chip guy Idontcare said competition is inefficient use of resources because you are essentially duplicating effort to do the same thing. However when a company gets big enough or successful enough they get complacent or build up enough bureaucratic layers that would make governments proud.

An article about Cyrix was saying how their chip was done with 1/10th the size of the manpower it takes at Intel. Also when both Intel/AMD's mantra was to take over the world, at Cyrix it was to make chips that are just good enough and lower cost and lower power.

Cause hey, you don't have to be a 100 billion dollar company to be called successful.
 
IntelUser2000 said:
That slide pops up in another of their article about IDF but it coincidentally happened to be the one I chose. Neither AMD nor Intel is doing that. It's the ARM world that embraced it first.
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The list on the right side of the slide reads like a check list for AMD's Zen:
  • CMP with 10s - 100s low power cores? Check (up to 64 cores right now, the cores are not low performance but very low power relative to the high power uncore. above 8 cores/after Zeppelin not CMP though by its strict definition of being a single die)
  • Full System-on-Chips? Check (for Intel this is still the domain of Atom whereas Core continues to require chipsets)
  • Servers, workstations, embedded...? Check
 
IntelUser2000 said:
GPU won't be fabbed in the same as I/O die because GPUs require high density and the benefits latest processes bring such as lower active power. I/O doesn't scale well with process shrink and doesn't need to be as fast so it uses ultra-low leakage and cheaper older processes such as 22FFL.
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Yeah that's my guess for Rocket Lake-S as well.

As for saying Lakefield is the future, its because low power Laptops and Tablets are the main market now.
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Similar products may find their way into the industrial Atom lineup and elsewhere . . . remember, Intel's real bread and butter is in the market they're losing to Rome. Though with the massive package sizes Intel can throw around at that level, we may not see Foveros used there. Just EMIB.

Foveros is a solution but an expensive one
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Do we know anything about the cost-side of implementing Foveros for a particular product?

Kosusko said:
Intel Atom C3958 @ 2.00 GHz (68,66%)
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That's . . . Denverton? Not really impressed but okay.
 
DrMrLordX said:
Do we know anything about the cost-side of implementing Foveros for a particular product?
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No, but engineering is always a compromise. There's no free lunch. Being able to use vertical 3D integration and connecting them all together in an ultra short and dense package is bound to be expensive.

They all serve a purpose with the slowest/highest power per bit/cheapest with organic MCM interposer, with EMIB somewhere in the middle, then Foveros.

The regular organic interposer packages are not expensive in absolute terms. For a 100mm2 class chip, I heard its something like $5 for the die and $5 for package. Of course doubling either or both will significantly cut into margins and net profits if talking about chips that are sold for $100 in Newegg. That means it might leave Intel at $60 or even lower. Those are just material costs. Don't forget there are others(R&D, maintaining facilities, paying people). Those costs take up 30% of Intel's entire revenue meaning it'll slice their 60% gross margin in half.

For Lakefield, they'll have to find two working dies, and connect them using a brand new method that uses ultra-fine connections to connect the two. It'll probably be expensive not just on a materials level, but because mass production will be limited by the difficulty of producing it.

Just as an example, the costs of using HBM are said to be expensive enough that it'll remain on low volume, high ASP datacenter products. Foveros is not going to be cheaper with even denser connections. Most industrial and SFF form factors are going to use Elkhart Lake and Jasper Lake with Tremont cores. Foveros brings no advantages in such cases.

That's . . . Denverton? Not really impressed but okay.
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Brief search shows about 25% perf/clock advantage compared to Goldmont Plus for the Zhaoxin.
 
IntelUser2000 said:
Don't forget there are others(R&D, maintaining facilities, paying people). Those costs take up 30% of Intel's entire revenue meaning it'll slice their 60% gross margin in half.
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Intel is paying those costs whether or not they use Foveros in any particular design. Well, R&D at least.

mass production will be limited by the difficulty of producing it.
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Do we know anything about how many units will enter the market? I understand Lakefield is supposed to be pretty niche.

Just as an example, the costs of using HBM are said to be expensive enough that it'll remain on low volume, high ASP datacenter products.
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But Raja said $200 for an Xe with HBM2!!!

(I kid, it's a joke)

Most industrial and SFF form factors are going to use Elkhart Lake and Jasper Lake with Tremont cores. Foveros brings no advantages in such cases.
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I would think Foveros would be handy for SFF form factors if Intel has problems producing dice with more than 4-6c Tremont configurations with acceptable yields. SFF package sizes are small enough that using EMIB promiscuously could be problematic. If they need larger core configurations (which they may not, admittedly), Foveros to the rescue?

Brief search shows about 25% perf/clock advantage compared to Goldmont Plus for the Zhaoxin.
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At least we know what is the VIA chip's real competition.
 
DrMrLordX said:
Intel is paying those costs whether or not they use Foveros in any particular design. Well, R&D at least.
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That's true. But they are usually evaluated in a per product basis. They abandon projects because they must have felt its not worth the R&D contribution.

Do we know anything about how many units will enter the market? I understand Lakefield is supposed to be pretty niche.
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It'll be limited in volume not just because the product not fitting in all markets(performance requirements) but small numbers of devices using it initially as manufacturers will test to see how the market reacts. I also cannot imagine dual screen devices being cheap. Even the Galaxy Book S was originally supposed to be a $999 device and that's a simple clamshell.

But Raja said $200 for an Xe with HBM2!!!

(I kid, it's a joke)
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Pfft. The ridiculousness of that when you consider how much Kaby-G(with single stack of HBM2) products were selling at retail.

I would think Foveros would be handy for SFF form factors if Intel has problems producing dice with more than 4-6c Tremont configurations with acceptable yields. SFF package sizes are small enough that using EMIB promiscuously could be problematic. If they need larger core configurations (which they may not, admittedly), Foveros to the rescue?
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It won't be an issue. Their small cores are pretty small. The 16 core Denverton is 120-140mm2 range with 16 cores. That's because each core is about 1/7th the size of Skylake.

Tremont is a far more capable core, but again they were emphasizing on die area efficiency, and part of the reason for clustered decode approach. Remember, the Package size of Lakefield is only 144mm2.

Cherry Trail 289mm2 package for 70mm2 die
A12, ~200mm2 package for 83mm2 die
SD855 ~154mm2 package for 70mm2 die
 
IntelUser2000 said:
ments proud.

An article about Cyrix was saying how their chip was done with 1/10th the size of the manpower it takes at Intel. Also when both Intel/AMD's mantra was to take over the world, at Cyrix it was to make chips that are just good enough and lower cost and lower power.
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i think that was centaur
 
IntelUser2000 said:
Cherry Trail 289mm2 package for 70mm2 die
A12, ~200mm2 package for 83mm2 die
SD855 ~154mm2 package for 70mm2 die
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Getting some preliminary guesses in for Tremont's core size. I'm guessing its in line with Goldmont and will be in the range of 1.2-1.4mm2. Looks like you'll also be able to fit 4-5 Atom-based cores in 1 Core-based core(sigh...) in the 10nm generation.
 
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IntelUser2000 said:
Getting some preliminary guesses in for Tremont's core size. I'm guessing its in line with Goldmont and will be in the range of 1.2-1.4mm2. Looks like you'll be able to fit 4-5 Atom-based cores in 1 Core-based cores(sigh...) in the 10nm generation.
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If Intel has 8-10 Core cores at the high-end of their consumer socket, does that mean that they could produce an 8x5 or 40-core Atom-based CPU, in the same silicon area? That would be interesting, as a competitor to AMD in the "moar cores" race. It wouldn't have the per-core grunt like Intel's full Core CPU architecture (Skylake, IceLake, etc.) does, but ... would it be marketable? 40-core CPU, for $300? Would that steal AMD's thunder, partially, for some workloads? Just think, it could be "Intel's BullDozer". You know that they're considering it, as an embedded chip for low-power servers.
 
VirtualLarry said:
If Intel has 8-10 Core cores at the high-end of their consumer socket, does that mean that they could produce an 8x5 or 40-core Atom-based CPU, in the same silicon area? That would be interesting, as a competitor to AMD in the "moar cores" race. It wouldn't have the per-core grunt like Intel's full Core CPU architecture (Skylake, IceLake, etc.) does, but ... would it be marketable? 40-core CPU, for $300? Would that steal AMD's thunder, partially, for some workloads? Just think, it could be "Intel's BullDozer". You know that they're considering it, as an embedded chip for low-power servers.
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To my understanding that 1.2 to 1.4 mm squared is just the core before the cache and everything else. Cache is a big size thing besides the actual core.
 
Roland00Address said:
To my understanding that 1.2 to 1.4 mm squared is just the core before the cache and everything else. Cache is a big size thing besides the actual core.
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I believe that size is with the L2 cache. Icelake is 6.9mm2 with the L2 and L3. Intel's 10nm cache sizes are 0.6mm2/MB. It's a bit more complicated with Lakefield since its a quad core module and it shares 1.5MB L2.

VirtualLarry said:
If Intel has 8-10 Core cores at the high-end of their consumer socket, does that mean that they could produce an 8x5 or 40-core Atom-based CPU, in the same silicon area?
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Maybe. Perhaps there are areas where it could be useful. But its what's called a "flock of chickens" approach, and even in servers doesn't work so well.

There's also an issue of power consumption. Cores can be very small nowadays but not as power efficient. Is Tremont more efficient than Sunny Cove? Sure. Is it 4-5x more? Likely not.

We know a 6 module(24 cores) microserver successor to Denverton that uses Tremont cores exist. The whole die is probably very small as well. Denverton was in the 110-130mm2 range. So there's that.

In the case of Lakefield, its extreme size and power requirements make Tremont useful. I'll further explain why if anyone wants.
 
Elkhart claimed to be 40% faster for CPU and 2x faster in graphics. Memory support improves from LPDDR4-2400 to LPDDR4-3200.

Can't say much about the CPU as its from an embedded roadmap and its clocks can be quite low. But the confirmation of the 32EU Gen 11 performing twice the 18EU Gen 9 is nice.

As expected the low end benefits disproportionately from architecture changes.
 
moinmoin said:
That's an improvement of 12.5%, that's not that much (especially considering the skipped Gen 10).
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That's incorrect reasoning.

You got 2x gains going from 24EU Gen 9 to 64EU Gen 11, while the bandwidth increased 55%. That's because things don't scale linearly.

Bandwidth increases only by 33% while the shader throughput increases by 77% for Elkhart Lake.

If you want double the performance in a balanced uarch, you need to double the bandwidth, the fillrate, and the shader throughput.

You agree yea?
 
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