In-regards to a revisit to the threading type used in FX-processors. Uncovered more of a timeline.
Sometime 2017 to September 2019: Planned to use the prior perpetual MIPS32/64 license then MIPS Open
After that in 2019 to Present: Moved to RISC-V ISA (which MIPS Open&8th gen MIPS eventually did as well)
Pretty sure it is a CMT design and will be using Opteron, FX, Sempron branding. In the same places as EPYC, Ryzen, Athlon respectively.
-RISC-V Opteron targets;
https://www.supermicro.com/Aplus/motherboard/Opteron3000/ <== AMD only has kept APU Opterons on site:
https://www.amd.com/en/opteron
-RISC-V FX target the prior FX markets but significantly reduced TDP.
-RISC-V Sempron target is probably extra low-TDP versions of FX.
This is a release of the Bitmanip specification intended for public review. Public review will be announced on the isa-dev mailing list and will close after 45 days. isa-dev: https://groups.google....
github.com
BMI/BMI2/TBM/ABM ?? and is in Public Review
This is the first release candidate for version 1.0 of the RISC-V vector extension for public review. This is not the frozen version of 1.0 for public review.
github.com
SVE ?? and is about to enter Public Review, eventually.
RISC-V Packed SIMD Extension. Contribute to riscv/riscv-p-spec development by creating an account on GitHub.
github.com
MMX/SSE/NEON ?? v0.95 - 06/07/2021
RISC-V cryptography extensions standardisation work. - riscv/riscv-crypto
github.com
LUT, AES, SHA, SM3, SM4 ?? v0.9.2 probably reliant on bitmanip and vector(etc/VAES/VSHA/VSM3/VSM4 forms)
Timeframe before actual announcement, the above all have to be frozen & ratified. Then, AMD would need to deploy $35,000 or higher to use RISC-V trademark/logo commercially.
Quesswork/Speculation:
Opteron-MD[Many Die] = 3D Processor: Up to six top dies(8-core/4-proc) and one bottom die(3x 64-bit DDR) => Below 2x315mm2 and above 315mm2
Operton/FX/Sempron -DD[Dual die] = 2.5D Processor: One 8-core/4-proc die and one IOD die(1x 64-bit DDR) => Seattle die size across two chips.
Opteron/FX/Sempron -SD[Single die] = Monolithic Procoessor: One 4-core/2-proc and integrated IO(1x 32-bit DDR) => Ontario die size
BD-XV -> This:
Critical Fast & Slow = LVT/HVT -> LVT/HVT (Same)
Non-critical Slow Path = RVT -> RVT (Same)
Non-critical Fast Path = RVT -> LVT (Different)
www.anandtech.com
Should be closer to Cortex-A57(use Hiroshige Goto image), Hence, the A1100 reference from above.