Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[eek2121]

Not true, or at least we don't know. Rembrandt is using FP7 for launch and we do not know when Rembrandt is coming to AM5.

AMD has already stated AM5 is launching with Zen 4.

Regarding Zen 4 lead times, /u/looncraz on reddit makes a very good point:

https://www.reddit.com/r/Amd/comments/t8fh4u/_/hzpx240

In short, lead times for N5 are much lower due to EUV, and the rumored April launch may actually be the date Zen 4 enters mass production.

The timeline makes perfect sense for an August or September launch.

 

[yuri69]

AMD has already stated AM5 is launching with Zen 4.

This is interesting from the AM5 launch PoV.

Recent desktop (OEM) APU launches followed the mobile launch in ~1Q. This doesn't seem to be the case with RMB and AM5. April getting rather close.

 

[jpiniero]

AMD has already stated AM5 is launching with Zen 4.

AMD has said nothing of the sort.


... When Rembrandt becomes available to DIY is another story.

 

[BorisTheBlade82]

Didn't Dylan already confirm they are using ASE FoCoS?

Well, in front of the Paywall he only stated that they would use InFo. So thanks for the information.
What do you folks think will be the advantages compared to the current packaging? Will it only help to prevent pad limitation or will it also improve J/bit? The vendor site mentions this but fails to explain to what they compare themselves.

 

[Justinbaileyman]

How close are we to a AM5 release with new motherboard's and CPU's?
I am looking at purchasing a 5950x as a up grade to my 3950x but also need to know if its even worth it at this point in time with AM5 right around the corner??

 

[soresu]

How close are we to a AM5 release with new motherboard's and CPU's?
I am looking at purchasing a 5950x as a up grade to my 3950x but also need to know if its even worth it at this point in time with AM5 right around the corner??

Minimum 4 months for a possible July release.

Bare in mind it's not just mobo and CPU, it's also DDR5 RAM which is potentially more expensive for the time being.

 

[Justinbaileyman]

Okay, thanks for the info. That seems like an awfully long time before we can get our hands on the new AM5 stuff..
Starting to lean more on snagging up a 5950x now.

 

[Markfw]

Okay, thanks for the info. That seems like an awfully long time before we can get our hands on the new AM5 stuff..
Starting to lean more on snagging up a 5950x now.

Lets put it this way, aside from loosing in gaming by a little, you won't regret the 5950x, its a screamer. Of course your 3950x is not that far away from a 5950x. Only in a few apps.

 

[uzzi38]

AMD has already stated AM5 is launching with Zen 4.

Regarding Zen 4 lead times, /u/looncraz on reddit makes a very good point:

https://www.reddit.com/r/Amd/comments/t8fh4u/_/hzpx240

In short, lead times for N5 are much lower due to EUV, and the rumored April launch may actually be the date Zen 4 enters mass production.

The timeline makes perfect sense for an August or September launch.

Just because publicly available rumours haven't suggested something doesn't mean it hasn't happened.

Again, not referring to anything in specific here, just point out that you can't just rely on rumours.

 

[eek2121]

AMD has said nothing of the sort.


... When Rembrandt becomes available to DIY is another story.

If I weren’t lazy I would dig up a source. Oh, right, they didn’t say ‘AM5’, they said next generation platform or some nonsense like that. Go look it up.

 

[jpiniero]

If I weren’t lazy I would dig up a source. Oh, right, they didn’t say ‘AM5’, they said next generation platform or some nonsense like that. Go look it up.

All they've said is that Zen 4 is coming to AM5. Which is true.

 

[moinmoin]

AM4 launched with Bristol Ridge. It's very likely that at the very least internally the first AM5 boards are tested primarily with Rembrandt. Whether and when there will be a DIY launch of it is up in the air though.

I wouldn't be surprised if AMD really did go with Samsung

I would. AMD is really close to TSMC, essentially getting treatment more similar to Apple and MediaTek than to Nvidia and Qualcomm, the latter two having to put in billions in prepayments to secure the amount of wafers they want.

I start wondering if he is just a second hand source though.

Leaks like that are always second hand. No first hand source would go public with its info, that would be suicide.

 

[jamescox]

Wouldn't they be able to test the chiplet and cache dies prior to bonding them?

I'm thinking that these would be chosen specifically for the desktop parts.

I don’t think they can be tested. The cache die are diced before bonding, so it is plausible that a cache die could be tested in some manner, but I don’t think the cpu wafer is diced before bonding. As far as I know, The cpu wafer is made, flipped over, and then thinned down to something like 20 microns. The cache die are placed into a reconstituted or carrier wafer and the whole thing is stacked on top of the cpu wafer. Then they dice the stacked wafer. So, no cpu testing until after bonding.

 

[igor_kavinski]

Doesn't seem like a fun process, especially if after going through all that trouble, the CPU fails validation.

 

[jamescox]

Eh, they will drop it once Zen 4 drops. I can’t see them spending time and money building the chips, testing them, and then not releasing them unless sales numbers for previous gen was way down.

We apparently get OEM only Threadripper pro (which effectively is Epyc), but still no regular Threadripper 5000. It is looking likely that it will not be released. I hope they have 3 sockets for Zen 4. It would be great if they could get the whole lineup out in a similar timeframe. Perhaps they will have sufficient 5 nm supply.

 

[Ajay]

Doesn't seem like a fun process, especially if after going through all that trouble, the CPU fails validation.

Well, yeah, there are several things that can fail, cache dice, cpu dice and the cold bonding process. Failure rates are multiplicative. So if 85% of CPU dice are good, and 95% of cache dice are good and 90% of bonds go well, then the net success rate would be ~73% good SoCs (or 27% fail rate). FYI, I just used random high percentages.

 

[yuri69]

Well, yeah, there are several things that can fail, cache dice, cpu dice and the cold bonding process. Failure rates are multiplicative. So if 85% of CPU dice are good, and 95% of cache dice are good and 90% of bonds go well, then the net success rate would be ~73% good SoCs (or 27% fail rate). FYI, I just used random high percentages.

No idea how well the semi industry handles this but usually there is also a transportation/mishandling-related failure rate related to each assembly step. I mean AMD has to ship the GF's IO dies to meet the TSMC's ones.

 

[Mopetar]

I don’t think they can be tested. The cache die are diced before bonding, so it is plausible that a cache die could be tested in some manner, but I don’t think the cpu wafer is diced before bonding. As far as I know, The cpu wafer is made, flipped over, and then thinned down to something like 20 microns. The cache die are placed into a reconstituted or carrier wafer and the whole thing is stacked on top of the cpu wafer. Then they dice the stacked wafer. So, no cpu testing until after bonding.

That makes sense, but is there anything stopping them from building something that can test an entire water before dicing? It doesn't even need to be extensive testing, just enough to know if cores would need to be disabled to meet a minimal speculation. Since they're dicing the cache they could still pick where it's applied after doing something like that.

The only reason not to is that doing that costs more than just slapping it together regardless. Since they're using the Zen 3D for both desktop and server there are plenty of configurations for the bonded die. I don't think the tooling gets any more complicated for the bonding process itself. It's just the extra cost of testing on both sides.

 

[Hitman928]

That makes sense, but is there anything stopping them from building something that can test an entire water before dicing? It doesn't even need to be extensive testing, just enough to know if cores would need to be disabled to meet a minimal speculation. Since they're dicing the cache they could still pick where it's applied after doing something like that.

The only reason not to is that doing that costs more than just slapping it together regardless. Since they're using the Zen 3D for both desktop and server there are plenty of configurations for the bonded die. I don't think the tooling gets any more complicated for the bonding process itself. It's just the extra cost of testing on both sides.

Testing chips before dicing up the wafer is definitely possible and can be automated to run the full wafer array if necessary (https://www.mjc.co.jp/en/technology/column/wafer_prober.html). It's typically some basic characteristic tests, but combined with the simulation info and location of the chip on the wafer, you can usually tell a lot about a chip before it ever gets cut from the wafer.

 

[DisEnchantment]

That makes sense, but is there anything stopping them from building something that can test an entire water before dicing? It doesn't even need to be extensive testing, just enough to know if cores would need to be disabled to meet a minimal speculation. Since they're dicing the cache they could still pick where it's applied after doing something like that.

The only reason not to is that doing that costs more than just slapping it together regardless. Since they're using the Zen 3D for both desktop and server there are plenty of configurations for the bonded die. I don't think the tooling gets any more complicated for the bonding process itself. It's just the extra cost of testing on both sides.

All Zen 2+ and above CCDs actually have an area designated for test probes/bumps which is being done before singulation. (grey area in this annotation)


That point you mentioned seems to be one of the main reasons why chip last 2/3D BE packaging is the only kind AMD seems to be interested in so far.
Because it allows to test everything before the final logic dies are packaged together.
CoWoS/EFB/Interposer are all chip last packaging tech. InFO is not, but some chip makers who can absorb the cost do that, because they can eat the loss due to defects or because their dies are small.

In chip first the wafer on which the logic dies are made is the carrier and packaging is done before singulation (i.e. InFO)

SoIC is CoW, but it is a FE packaging, it is also done before singulation so they need to probe before bonding, otherwise they will take some loss.

 

[maddie]

Testing chips before dicing up the wafer is definitely possible and can be automated to run the full wafer array if necessary (https://www.mjc.co.jp/en/technology/column/wafer_prober.html). It's typically some basic characteristic tests, but combined with the simulation info and location of the chip on the wafer, you can usually tell a lot about a chip before it ever gets cut from the wafer.

Simple reasoning can tell us that they do test before assembling the CPU. How else can you bin for Epic to enable the performance range. This was in an AMD paper/patent on allowing a wider performance range of high core count CPUs by using binned chiplets vs a monolithic die.

 

[NostaSeronx]

On the ongoing following of GlobalFoundries nodes. If Family 19h is backported to GlobalFoundries. It will most likely be using GlobalFoundries upcoming unannounced 12nm Ultimate High Performance; Strained Nanosheet process. Which succeeds the 14HP node, while gobbling up the 14LPP/12LP/12LP+ node.

Origin:
It is derived from the 2009 GAA-SOI from STMicroelectronics/CEA-Leti and 2015+ derivative work between GloFo/STM/Leti for Fin-on-ins to GAA-on-ins. Heavy price reduction for Fin on SOI means lower cost of GAA's improvement over expensive bulk Fins.

The 2009 STM's GAA-bulk look, the SOI variant in the research paper is only shown in example and simulated.

Given a new node that has high linear Vdd scaling over Fin. 14LPP-12LP+ Vdd-nom = 0.8V while 12UHP Vdd-nom = 1.1V, with the Undervolt to 0.8V Vddnom seeing a huge boost over prior 14nm/12nm node; basically above double Frequency potential at 0.8V and over 50% between 1.1V to 1.5V.

It is my opinion that Zen3-Monet is not likely to happen instead will be Zen4.
12LP+ Old 12nm => Zen3 backport
12UHP New 12nm => Zen4 backport
There is no reason not to support AVX512 at GF. Giving a full stack down the road for x86-64-v4: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL.

Athlon "Monet" APU/Old GF 12nm -> Athlon "? Point" APU/New GF 12nm
Especially with more Zen4 models identified than Zen3 models. Which more or less means if there is a back port, it is going to be Zen4 ISA rather than Zen3 ISA.


Both 12nm Ultimates, 12ULP(formerly 12FDX: 10nm Planar-SOI on 12nm BEOL) and 12UHP(formerly 10-12NSH; 10nm Stacked Nanosheet-SOI on 12nm BEOL). Support the below dimensions:
Minimum Polypitch = 64nm (both nodes have continuous poly pitch up to 84CPP)
Minimum Metalpitch = 56nm

Both share tensile Si strained SOI wafers. With the frequency improvements collected from R&D Logic:
Bulk 10nm Fin FEOL = Base
SOI 10nm Fin FEOL = +30% Freq over 10nm Bulk Fin
Planar-SOI 10nm = +20% Freq over 10nm Bulk Fin.
Planar-SSOI 10nm = +60 Freq over 10nm Bulk Fin.
Old Albany SSOI 10nm Fin FEOL = +60% Freq over 10nm Bulk Fin
New SSOI 10nm GAA FEOL = +90% Freq over 10nm Bulk Fin

With that GlobalFoundries FinFETs last standard production out is July 2023 and last pre-ordered production out is January 2025. GlobalFoundries announcing switching to GAA from Fin soonish. Since, the GF-affliated papers for 12ULP(sSOIUTB-FET) and 12UHP(sSOIGAA-FET) have been released. There is no customer demand at GlobalFoundries for anything below 56p BEOL till ~2035. So, Perf/Power scaling is done by materials and transistors while keeping/increasing customers by doing what no other fab is achieving. AMD in this is increasing employees assigned at GF Fabs. With Fab7 having the largest increase while having no new node announced yet.

With the Zen4 backport supposedly entering the market as Gen2 after the "Athlon/Sempron Budget/Ultra-budget Desktop Platform 2023+". I don't think anyone is expecting a budget Zen4 APU at GlobalFoundries before Zen4 APUs at TSMC launch. 2022-Z4CPU(non-monolithic IGFX) -> 2023/4-Z4APU(monolithic IGFX) -> 2025-Z4BudAPU(lower density monolithic IGFX).

At launch with non-harvested parts Ultra-budget SEP $20-$40 and Budget SEP $40-$80 => Exclusively at GlobalFoundries.
Budget succeeds Zen Pollock(64-bit DDR4) at GF with Zen4 Point APU(64-bit DDR5) at GF, in turn competing against the new high-end N-lineup at Intel:
soc/intel/alderlake: Add Alder Lake N memory data bus width
Alder Lake N has single memory controller with 64-bit bus width. <== Feeds 8E cores + 32EUs

I have only found mentions of the Budget desktop platform. However, it doesn't indicate if it is socketed LGA/PGA or embedded BGA desktop. I believe the market has doomed a low-end socket so it most likely AMD APU on Board(embedded BGA) for Desktops.

On hard speculation, I would suspect Zen4 on GF would be flipped relative to standard Fam 19h:
Standard TSMC Fam 19h => 4x Scalar ALU + 6x 256-bit SIMD ALU -> More Server/HPC focus
New Lightweight GF Fam 19h => 6x Scalar ALU + 2x 256-bit SIMD ALU -> More Online/Casual focus

 

[Mopetar]

Simple reasoning can tell us that they do test before assembling the CPU. How else can you bin for Epic to enable the performance range. This was in an AMD paper/patent on allowing a wider performance range of high core count CPUs by using binned chiplets vs a monolithic die.

It wasn't a question of testing before assembly. We already know they do that and always have because they used dead dies on some products to stabilize the heat spreader.

Rather it was a question of whether or not they could test the dies while they were all still part of the same wafer so that the cache layer could be selectively applied only to good dies.

 

[nicalandia]

Following Up on this Rumor that Bergamo will have a 16C/32T Zen4C Chiplets with Only L2$ and 64 MiB of L3$ On Top of 8 Core Segment.

AMD Ryzen 7000 'Raphael' 5nm Zen 4 Chiplet Layout Suggest Up To 16 Cores Per Die With 64 MB L3 Cache Moved To Vertical Stacks

An alleged diagram of AMD's next-gen Ryzen 7000 'Raphael' CPU's chiplet layout featuring up to 16 5nm Zen 4 cores has leaked out.

wccftech.com

This is The actual size comparison of a 67 mm^2 8C/16T Chiplet with Full 32MiB of L3$ and a 16C/32T 64 MiB 3D V Cache Mock Up, the size is about 70 mm^2



The Red Square is where the 3D V Cache will sit the TVS Area in Green are used as interconnect ring for the L3

 

[DrMrLordX]

Huh. If that's true then that would explain why AMD has delayed Raphael for so long. They're not sharing CCDs with Genoa anymore. They're possibly sharing a CCD layout with Bergamo.