Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

Vattila

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Oct 22, 2004
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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

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What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! :)
 
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Tuna-Fish

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Mar 4, 2011
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jpiniero said:
They are cutting density with N3E??? That's a new one.
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They have done this before, see N6 which is actually a later node than the initial N5, but it could be done on mostly the same equipment as the N7, and had better yields.

I think in the future we are going to see more and more products on these "scaled-back high-end" nodes, simply because of cost-efficiency.
 
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jpiniero

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Tuna-Fish said:
They have done this before, see N6 which is actually a later node than the initial N5, but it could be done on mostly the same equipment as the N7, and had better yields.
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Not really the same thing since as you mentioned it's an upgrade from N7. N3E sounds like it's a wholesale replacement for N3 and N3 might have a very short lifespan because of it.
 
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moinmoin

moinmoin

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jpiniero said:
They are cutting density with N3E??? That's a new one.
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Intel's +-series of halfnodes were all about trading density for other more desirable qualities. N3E seems to be along that way. So you meant new one for TSMC?

jpiniero said:
Not really the same thing since as you mentioned it's an upgrade from N7. N3E sounds like it's a wholesale replacement for N3 and N3 might have a very short lifespan because of it.
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Is N7+ still in use? That one seemed to be an unpopular node that never got out of the shadows of the more popular N7, and the later N7P and N6 nodes effectively replaced it.
 
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Doug S

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jpiniero said:
Not really the same thing since as you mentioned it's an upgrade from N7. N3E sounds like it's a wholesale replacement for N3 and N3 might have a very short lifespan because of it.
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I look at N3E as being another N6 or N4 - an enhanced cheaper version of the previous process that's the long term target. They may or may not have an "N3P" equivalent - they might figure it is better to move to GAA with N2 where performance gains are easier to squeeze out.

While they still make N7 and N5 wafers down the road, their preference is for customers to move long term designs to N6 or N4 as it is cheaper for them to make and they pass that savings along to customers. I view N3E as being the same thing, they will still make N3 wafers for those who want them but if the node timing has left Apple off N3 they won't have Apple's usual medium term sticking by the original node (i.e. they are still buying N7 wafers, and did not move those designs to N6)

TSMC would have called N3E "N2" had they not run out of integers and used N2 already for a new process generation. I wouldn't be surprised to hear them officially designate what has been called "N2" with some other name containing more digits like Intel did for its "angstrom" thing. Maybe P2000 to reflect picometers and one up Intel :tongueclosed:
 
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Doug S

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jpiniero said:
If Apple doesn't use N3 for the 2023 iPhone there might not be any customers for it other than Intel.
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Apple may be using it for some Apple Silicon stuff or Apple Watch SoCs. The timing only matters to them for the iPhone, not the rest of their product line (though of course the rest of their product line is maybe a quarter of the wafer starts used for iPhone SoCs)
 
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Frenetic Pony

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jpiniero said:
Not really the same thing since as you mentioned it's an upgrade from N7. N3E sounds like it's a wholesale replacement for N3 and N3 might have a very short lifespan because of it.
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Well, if N3 really is as delayed and has as bad yields as rumored, then the practical move is just to make something that works. If that note about N3E is correct, then it appears that's the node that actually works from yield standpoint.

Makes me question Intel's brazen roadmap for nodes certainly. If TSMC, historically the best at delivering targets, can't get to it's own with a bigger CAPEX than Intel then perhaps Intel is in equal trouble. Not that this would be the first time anyone's questioned Intel's recent roadmaps.

But bringing it back around to Zen... Here's a hypothesis: Future node shrinks are becoming irrelevant for a large class of consumer hardware. Density is becoming so high that "good enough" performance can squeeze into more and more monolithic designs/chiplets. Meanwhile larger designs can be cut up into more and more chiplets. Thus things like power delivery, power efficiency, and packaging will become far more important than ever increasing density.

I wouldn't be surprised if AMD really did go with Samsung for a large portion of consumer/mobile chips starting next year or 2024. Samsung's 3nm looks fairly competitive with TSMC's in terms of power efficiency, if not density, but as stated above for like... an 8 core CPU and a chiplet GPU this probably doesn't matter much. I'd also guess that AMD might be more interested in TSMC's 4x and wafer on wafer power delivery stacking for say, CDNA4 than in 3NE. Just adding more chiplets you can clock way higher for a super high power draw product like CDNA makes more sense than trying to get more transistors onto the same chiplet. Since you can go past the reticle limit anyway who cares?

Makes me wonder what server CPUs might best be built on. They need high power efficiency, high density to pack as much CPU power into a socket as possible to lower total cost of ownership, competitive pricing, etc.
 
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leoneazzurro

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AMD is selling everything they can produce, if they are not concentrating on the desktop it's because they redirected the production on the much more lucrative server market. Better selling four 800$ 5950X or one $6000+ Milan, margin-wise?
 
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uzzi38

uzzi38

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deasd said:

Since AM5 is LGA package, would AMD had move their package processing from original factory to other places?
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LGA vs PGA doesn't change much at all, I was referring more to if they're sticking to organic substrate for the packaging technique or instead doing something different.

And for the record, I'm saying this just to put up the idea, this isn't me talking about rumours or anything.
 
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Justinus

Justinus

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uzzi38 said:
LGA vs PGA doesn't change much at all, I was referring more to if they're sticking to organic substrate for the packaging technique or instead doing something different.

And for the record, I'm saying this just to put up the idea, this isn't me talking about rumours or anything.
Click to expand...

Ah but if AMD is indeed gearing up to release more zen 3 skus for longer term, perhaps they are not converting any lines in the current zen 3 plant to zen 4 packaging and instead using another plant altogether? Why convert active zen 3 production lines when you plan to continue zen 3 production?

How many packaging plants does AMD use now? Is EPYC/TR done in a different plant from mainstream? Is zen 2 and zen 3 done in the same or different plants? Is it based on socket/substrate? I have no idea.

This is entirely baseless speculation
 
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