Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Timorous]

AMD ALREADY has the outright performance crown. Gaming, laptop, server, HEDT, and the closest Intel gets is desktop space, and that is arguably the best case scenario for Intel, a tie.

give me a few grams of whatever you're using.

I meant raptor lake refresh where I expect the 14900K to eek out a slight jack of all win Vs the X3D. Slightly ahead in all core MT and slightly ahead in gaming but with worse power draw.

If AMD decide they want to crush it they have the components to make such a part relatively easily.

 

[A///]

I meant raptor lake refresh where I expect the 14900K to eek out a slight jack of all win Vs the X3D. Slightly ahead in all core MT and slightly ahead in gaming but with worse power draw.

If AMD decide they want to crush it they have the components to make such a part relatively easily.

14900k aka tarted out 13900k will only win against base zen 4, the zen 4 3d parts have too high a performance gap in games where their cache gets hit for it to matter. we're talking 40-50 gps difference in some games. without raising power and clocks through the roof intel is not gonna get there and amd has no reason to work on an xt processor when their teams are better spent readying zen 5 while supporting zen 4. not to mention the other team working on zen 6 and 7.

the 14900k may be the most useless refresh in existence based on how little we know. I think it'll be a poorer seller than raptor lake.

 

[Saylick]

Super impressed that AMD were able to shrink Zen 4 so much when it's on the same node. Just blows my mind that the Branch Predictor and mOp cache were condensed so much, especially when both are mostly just cache.

 

[Timorous]

14900k aka tarted out 13900k will only win against base zen 4, the zen 4 3d parts have too high a performance gap in games where their cache gets hit for it to matter. we're talking 40-50 gps difference in some games. without raising power and clocks through the roof intel is not gonna get there and amd has no reason to work on an xt processor when their teams are better spent readying zen 5 while supporting zen 4. not to mention the other team working on zen 6 and 7.

the 14900k may be the most useless refresh in existence based on how little we know. I think it'll be a poorer seller than raptor lake.

13900K can trade blows with the 7950X3D in both MT and gaming. Sometimes the 13900K wins others the 7950X3D wins.

Also Factorio and Stellaris type games seem to hit a point where they will eventually saturate the extra cache and then performance normalises.

One of the few more mainstream reviews that actually tests Stellaris using a late game save test.

So I do expect the 14900K to be faster than the 7950X3D on average at 1080p and faster in some MT workloads. I also expect further refinement of the IMC to allow for even higher clocking ram which does benefit Raptor Lake quite a bit.

It will do this with far worse power characteristics mind but for some people all that matters is peak performance in their app/game of choice.

Should AMD deem it worthwhile they can crush the 14900K in MT and atleast match it in gaming with slightly better bins or by inverting the stack so it is cache on the bottom.

 

[A///]

13900K can trade blows with the 7950X3D in both MT and gaming. Sometimes the 13900K wins others the 7950X3D wins.

Also Factorio and Stellaris type games seem to hit a point where they will eventually saturate the extra cache and then performance normalises.

One of the few more mainstream reviews that actually tests Stellaris using a late game save test.

So I do expect the 14900K to be faster than the 7950X3D on average at 1080p and faster in some MT workloads. I also expect further refinement of the IMC to allow for even higher clocking ram which does benefit Raptor Lake quite a bit.

It will do this with far worse power characteristics mind but for some people all that matters is peak performance in their app/game of choice.

Should AMD deem it worthwhile they can crush the 14900K in MT and atleast match it in gaming with slightly better bins or by inverting the stack so it is cache on the bottom.

The problem with a lot of these gaming charts is there's no agreed normal range. each site has their own results. Last week someone posted charts putting the 7950x3d well ahead of the 13900k in games where that l3 cache mattered most.

there would be no point in amd wasting time money and manpower to make a refesh. the intel refresh is a minimal effort refresh. it'll debut at the same $600+ price as the 13900k did. zen 4 is cheaper now. they already have the advantage. people on 12th gen aren't going to upgrade to 14th, they'll wait for arrow lake. you can keep arguing that amd should do this or that when they're outselling intel 2 or 3 to 1.

 

[H433x0n]

there would be no point in amd wasting time money and manpower to make a refesh. the intel refresh is a minimal effort refresh. it'll debut at the same $600+ price as the 13900k did. zen 4 is cheaper now. they already have the advantage. people on 12th gen aren't going to upgrade to 14th, they'll wait for arrow lake. you can keep arguing that amd should do this or that when they're outselling intel 2 or 3 to 1.

I don't think it'd hurt to make something like an R7 7800X or a R9 7950XT, I'm a hardware nerd so my viewpoint probably doesn't represent the average consumer. I don't think releasing either of those products would make financial sense if Zen 5 is still set to release in Summer of 2024. I agree on Raptor Lake refresh probably doing some brand damage, especially when I see the motherboard vendors beefing up VRMs and talking about the next generation pushing power consumption even further. If they were to keep the same upper end power limit (253W) and take advantage of the enhanced efficiency from DLVR and Intel 7 updates, it could be more interesting but I know that's not the route they'll take. Zen 4 is not outselling RPL, although Zen 3 appears to still have strong sales.

 

[A///]

I don't think it'd hurt to make something like an R7 7800X or a R9 7950XT, I'm a hardware nerd so my viewpoint probably doesn't represent the average consumer. I don't think releasing either of those products would make financial sense if Zen 5 is still set to release in Summer of 2024. I agree on Raptor Lake refresh probably doing some brand damage, especially when I see the motherboard vendors beefing up VRMs and talking about the next generation pushing power consumption even further. If they were to keep the same upper end power limit (253W) and take advantage of the enhanced efficiency from DLVR and Intel 7 updates, it could be more interesting but I know that's not the route they'll take. Zen 4 is not outselling RPL, although Zen 3 appears to still have strong sales.

They did an XT already 2 gens ago. it sold poorly not because of the performance gain being next to nothing but because the original hardare came down in price and the xt went back to launch prices. why would you pay for a slightly faster chip now if you can hold out for 8-10 months and get the zen 5?

some of you have a hard on at the idea of amd releasing a refreshed chip that doesn't make sense. there's always something good coming out. you gonna buy every 6-8 months?

 

[igor_kavinski]

there's always something good coming out. you gonna buy every 6-8 months?

Wouldn't it be nice if AMD did do that, for something like $200 a year hardware refresh subscription? Out with the old, in with the new. People who don't subscribe pay $300 extra for the latest and greatest. This way, AMD makes $800 per socket during its lifetime from a single user. I bet 95% of affluent gamers/enthusiasts wouldn't bat an eye at such a deal. What could be more fun than enjoying a swanky new CPU for a year, then get a new package from AMD, with shiny new one giving 15% extra perf minimum?

 

[Abwx]

. If they were to keep the same upper end power limit (253W) and take advantage of the enhanced efficiency from DLVR and Intel 7 updates, it could be more interesting but I know that's not the route they'll take. Zen 4 is not outselling RPL, although Zen 3 appears to still have strong sales.

There s a misconception here about what is DLVR.
It increase efficiency at average loadings when all cores are not used at max frequency, at max perf efficency wont change in respect of the previous design that had DLVR disabled, assuming of course that it was physically present, if it wasnt and is implemented only starting from the refresh then efficency will decrease at max loading by some amount.

FTR such a voltage regulation is implemented in AMD s designs since Zen 1.

 

[A///]

There s a misconception here about what is DLVR.
It increase efficiency at average loadings when all cores are not used at max frequency, at max perf efficency wont change in respect of the previous design that had DLVR disabled, assuming of course that it was physically present, if it wasnt and is implemented only starting from the refresh then efficency will decrease at max loading by some amount.

FTR such a voltage regulation is implemented in AMD s designs since Zen 1.

then how does dlvr allegedly help inteo in future processors such as raptor refresh if it's there? does it take into account 2-3 cores being at the upper most boost and other cores not hitting the all core boost speed and switching the power savings on cores and alternating every few seconds as cores loose boost before regaining?

 

[Timorous]

there would be no point in amd wasting time money and manpower to make a refesh.

Swapping the standard 8c CCD in the 7950X3D for a 16c Zen4c CCD seems to be about as low effort as you can get. Far lower effort than RPL refresh.

It wouldn't be a refresh for AMD at all, just a new SKU at the top of the stack. Everything else has already dropped in price to be pretty much 1 tier below where it started so a new SKU at the top of the stack is all that AMD may decide to do.

some of you have a hard on at the idea of amd releasing a refreshed chip that doesn't make sense. there's always something good coming out. you gonna buy every 6-8 months?

It would be an entirely new SKU, not just the same SKU with a better bin. That is not a refresh but a new product ala 5800X3D. Would also be a chance for AMD to work out any issues with such a mixed design sooner rather than later.

If Arrow Lake is strong then I expect AMD will need such a part in the Zen5 lineup.

 

[Abwx]

then how does dlvr allegedly help inteo in future processors such as raptor refresh if it's there? does it take into account 2-3 cores being at the upper most boost and other cores not hitting the all core boost speed and switching the power savings on cores and alternating every few seconds as cores loose boost before regaining?

Say a 8P configuration with 2 cores at full frequency and 6 core at 50% of max frequency.
Without DLVR all cores are fed with the same voltage, say 1.2V and let s assume that power at max frequency for a single core is 30W.

2 cores will use 60W while the 6 remaining ones will use 6 x 15 = 90W, for a total of 150W for the 8 cores.

The 6 cores used at 50% require actually 0.8V to work at 50% frequency, so a resistance is connected in serial with the supply rail such that the voltage is brought down from 1.2V to 0.8V, this reduce the 6 cores power to 90/(1.5^2) = 40W instead of 90W.

But there s also the serial resistance to consider and it dissipate 20W, so the 6 cores comsumption + serial resistance will be reduced down to 60W instead of 90W and the 8 cores will hence use 120W instead of 150W.

Said serial resistance is made of parralleled mosfets whose conduction is set accordingly to the cores frequencies, at full throughput the mosfets are rendered fully conductive and all cores will be fed with 1.2V, so there s no power saving at full frequency boost, only at average loading when some cores will require less voltage.

Edit : AMD did call this implementation Linear Voltage Regulator, wich it is even if the mosfets are used in switching mode, Intel for marketing reasons added the term Digital but there s nothing digital actually, that s the same high speed switching of mosfets that charge a capacitor and the whole is akin to a classical linear non switching regulator.

 

[A///]

Swapping the standard 8c CCD in the 7950X3D for a 16c Zen4c CCD seems to be about as low effort as you can get. Far lower effort than RPL refresh.

It wouldn't be a refresh for AMD at all, just a new SKU at the top of the stack. Everything else has already dropped in price to be pretty much 1 tier below where it started so a new SKU at the top of the stack is all that AMD may decide to do.

and lose cache in the process. the 7950x3d employs dual zen4 ccds. one comes with the l3 $ on top, correct? Removing the normal ccd leaves with you less overall cache. it won't be noticeable in gaming either way because you'd use ryzen master to park the non l3 $ ccd. in other applications where both ccds get hit you'd see a performance difference.

the 16c zen4c ccds are meant for epyc and epyc is a much higher margin product for amd. amd won't waste the time and money to develop a chip as you propose for ryzen mainstream. why what is the point? the margins on those ar emuch smaller than epyc and to an extent the threadrippers. epyc is a money printing machine. why waste time when intel again as I repeat this again is being outsold in the diy desktop space by an already large margin?

 

[A///]

It would be an entirely new SKU, not just the same SKU with a better bin. That is not a refresh but a new product ala 5800X3D. Would also be a chance for AMD to work out any issues with such a mixed design sooner rather than later.

If Arrow Lake is strong then I expect AMD will need such a part in the Zen5 lineup.

uh huh. hate to bring this up again because it pissed the intel people off like harry but intel's 13900k needs 24 cores total to even match or slightly surpass in some very niche cases a 16 core amd processor operating at a slightly lower speed and running much cooler to boot when pushed to the limits. intel would need to move mountains for arrow lake to be 1 to 1 competitive with amd. zen 5 is not meant to be a small bump in performance. this has been discussed to high heaven for a while now. arrow lake as it stands is sstill gonna be a 8+16 product with the addition of +2 for the soc cores i believe. if the st and mt performance are marginally ahead of zen 5 a year from now, that' ain't impressive. especially as it will most certainly being power hungry compared to zen 5. If intel was so damn great they'd stick with 16 big cores on their tiled approach and get power use down similar to zen 5. the e cores do some lifting in the background but they're largely useless for most tasks that can't offload to them. and intel needs 24 of them to get slightly ahead in multi over 16 cores.

the 13900ks brings even more st and mt performance at the cost of more heat and more power. next gen's performance will be paramount due to more mature ddr5. there's a sweet spot for ddr5 that mod @Shmee posted a while back or someone else in the gaming or video card threads showing what speed of ddr5 needs to be to match very high end very fast ddr5 and we're quite close to it now. Another generation and we'll surpass ddr4 speeds with the benefits of ddr5. In a leak from last week I saw Raptor's refresh getting a 6400 sped capable imc. that's an alright speed, it's still 1000 and more in difference to where it should be but it's a start. I expect zen 5 and arrow imcs to operate in the low to mid 7000's and operate in the low 8000's with better kits.

 

[A///]

Say a 8P configuration with 2 cores at full frequency and 6 core at 50% of max frequency.
Without DLVR all cores are fed with the same voltage, say 1.2V and let s assume that power at max frequency for a single core is 30W.

2 cores will use 60W while the 6 remaining ones will use 6 x 15 = 90W, for a total of 150W for the 8 cores.

The 6 cores used at 50% require actually 0.8V to work at 50% frequency, so a resistance is connected in serial with the supply rail such that the voltage is brought down from 1.2V to 0.8V, this reduce the 6 cores power to 90/(1.5^2) = 40W instead of 90W.

But there s also the serial resistance to consider and it dissipate 20W, so the 6 cores comsumption + serial resistance will be reduced down to 60W instead of 90W and the 8 cores will hence use 120W instead of 150W.

Said serial resistance is made of parralleled mosfets whose conduction is set accordingly to the cores frequencies, at full throughput the mosfets are rendered fully conductive and all cores will be fed with 1.2V, so there s no power saving at full frequency boost, only at average loading when some cores will require less voltage.

Edit : AMD did call this implementation Linear Voltage Regulator, wich it is even if the mosfets are used in switching mode, Intel for marketing reasons added the term Digital but there s nothing digital actually, that s the same high speed switching of mosfets that charge a capacitor and the whole is akin to a classical linear non switching regulator.

Thank you for the information and thorough explanation. It doesn't explain why people are assuming this will allow intel to push clocks higher on desktop because they figured out how to get their implement working on desktop or it was process related and I'm misremembering. I recall amd mentioning pairing their lvr approach with a future microcode or in os software solution to pause parts of the processor when not in use to further reduce power but that was strictly about mobile. If they see intel mplement it in desktop and are successful we may see it on desktop too for amd. the feature as you explained seems to be more useful for mobile but it may be worth while on desktop if you consider that not everyone is spending their compute time with their processors at max boost. the current windows power plans are dated due to how they operate but it would be interesting to see how dlvr for intel or amd lvr would handle on desktop when set to low power mode. low power mode will only engage the processor in higher speeds if called for, but if you could drop the power use by 1/3 or 1/2 in low power mode doing basic tasks like emails or playing music locally it would make a big difference in power outlook for businesses that upgrade given countries ar ebecoming more strict with power usage in corporate nevironements.

 

[Timorous]

and lose cache in the process. the 7950x3d employs dual zen4 ccds. one comes with the l3 $ on top, correct? Removing the normal ccd leaves with you less overall cache. it won't be noticeable in gaming either way because you'd use ryzen master to park the non l3 $ ccd. in other applications where both ccds get hit you'd see a performance difference.

the 16c zen4c ccds are meant for epyc and epyc is a much higher margin product for amd. amd won't waste the time and money to develop a chip as you propose for ryzen mainstream. why what is the point? the margins on those ar emuch smaller than epyc and to an extent the threadrippers. epyc is a money printing machine. why waste time when intel again as I repeat this again is being outsold in the diy desktop space by an already large margin?

A proposed 24c 7955X3D would have more cache. 1 ccd with 96MB of L3 and 8MB of L2 and the other with 32MB of L3 and 16MB L2. Vs the 16C 7950X3D which has 1 CCD with 96MB L3 and 8MB L2 + 1CCD with 32MB L3 and 8MB L2.

Most high MT desktop workloads are not that cache sensitive which is why the vanilla 7950X is slightly better than the X3D for purely productivity workloads. This 7955X3D would be a good step faster in those workloads than the 7950X while keeping the top tier gaming performance of the 7950X3D.

I doubt every Zen4c CCD will bin with the required v/f curve to be used in Bergamo SKUs. Any that don't will be ideal for such a Ryzen SKU should AMD decide to make one.

Whether AMD bother depends on a variety of factors we are not privy to but they do absolutely have the option to release something should those factors indicate it is worthwhile.

 

[Abwx]

Thank you for the information and thorough explanation. It doesn't explain why people are assuming this will allow intel to push clocks higher on desktop because they figured out how to get their implement working on desktop or it was process related and I'm misremembering.

Overall DLVR is of great benefit in mobile with say a core pushed at max frequency and all others running at 20% or so FI.

In the exemple i gave the 30W spared in the 6C can be used to boost the two high clocked cores to higher frequencies, so clocks can be pushed higher but not on the whole cores, same if 4C are used at max frequency and the four other at 10-50%.

As to why people expect the whole cores to gain frequency at same power is because they dont know what is a DLVR...

 

[A///]

A proposed 24c 7955X3D would have more cache. 1 ccd with 96MB of L3 and 8MB of L2 and the other with 32MB of L3 and 16MB L2. Vs the 16C 7950X3D which has 1 CCD with 96MB L3 and 8MB L2 + 1CCD with 32MB L3 and 8MB L2.

Most high MT desktop workloads are not that cache sensitive which is why the vanilla 7950X is slightly better than the X3D for purely productivity workloads. This 7955X3D would be a good step faster in those workloads than the 7950X while keeping the top tier gaming performance of the 7950X3D.

I doubt every Zen4c CCD will bin with the required v/f curve to be used in Bergamo SKUs. Any that don't will be ideal for such a Ryzen SKU should AMD decide to make one.

Whether AMD bother depends on a variety of factors we are not privy to but they do absolutely have the option to release something should those factors indicate it is worthwhile.

You'd still park one ccd down because you'd be dealing with the if delays if data gets pushed to the not so useful ccd. upping one ccd to 24 cores as you said in another thread 8+16 won't offer you much. most games struggle to take advantage of 8 cores, but if your remaining 16 cores are cacheless and single threaded you're not doing yourself any favors and are contributing to heat. At best you'd get similar if not same performance as Intel. For that to be worth it the c cores would have to be shrunken down zen 5 or zen 6 cores with cache and with smt to make it useful. if there was a hard cut off of power delivered to each core through the bios that would help in the way of power management and thermals. The 8+16 ccd doesn't make sense for amd unless they can fix the issues intel has and improve, but also if they can find a reason to make it at volume. Again I'm repeating myself for the 10th time in the past year. none of this makes sense if epyc can't use it. epyc is a money maker. Epyc is a high margin product. consumer ryzen is not where the large bulk of their income is. they have to sell more units of consumer ryzen to get the margins that epyc gives them. Youre 8+16 proposition also makes no sense because it would be ideal to include 2 of those ccds with one having the L3 $ on it. why do you ask? because if they make such a ccd from the top, their threadrippers and epycs get a major bump in core counts. they won't have a complain about core counts for years. it'll also force intel to address their short comings and figure out how to get their issue of ht and avx512 working on their processors.

Realistically this is likely to never happen because 8+16 is a lot more complicated than 8 normal cores from a fabrication perspective, otherwise you add time to your binning and your production rate slows down as a result, and for a company like amd that is almost always supply constrained because companies want their products by the truck load, it's a terrible idea.

 

[A///]

As to why people expect the whole cores to gain frequency at same power is because they dont know what is a DLVR...

It may come from dlvr discussion overshadowing the general maturing progression of a production node opening avenues up. Although it's a non issue here. raptor lake's refresh won't be worth the materials it's made of.

 

[Ajay]

It may come from dlvr discussion overshadowing the general maturing progression of a production node opening avenues up. Although it's a non issue here. raptor lake's refresh won't be worth the materials it's made of.

Well it will be, just at what price (/profit). Zen5 is going to come along and make it second choice by a fair bit. Mike Clark was sure excited about Zen5 - but my guess is that that was more on the server side, and less so on the 'second class' desktop side.

 

[soresu]

…and half the L3 cache

Assuming they do not just readdress this with 3D cache stacking in future iterations which seems very possible, at least when it is used in the server space.

 

[soresu]

Super impressed that AMD were able to shrink Zen 4 so much when it's on the same node. Just blows my mind that the Branch Predictor and mOp cache were condensed so much, especially when both are mostly just cache.

AMD previously took lessons learned from the compact Bobcat/Jaguar to design the final BD iteration Excavator before applying it to the design of Zen1 in their own words.

It would not surprise me if eventually the Nc core design lesson spill over into the main core design, albeit likely not until at least Zen6.

 

[soresu]

Not sure if anyone actually posted this, seems worth posting if not:

 

[A///]

Well it will be, just at what price (/profit). Zen5 is going to come along and make it second choice by a fair bit. Mike Clark was sure excited about Zen5 - but my guess is that that was more on the server side, and less so on the 'second class' desktop side.

Raptor lake refresh is this august or september, zen 5 will likely be mid to late 2nd half 2024 product. at which time arrow lake launches. I'm not sure what you're even on about here. most people aren't going to buy zen 5 right away if intel's product is anywhere from 1 month to 3 months away if they want to see where intel stands when arrow lake comes out. amd's bom is certainly lower than intel's but amd still has to pay for that research and increasing wafer costs from tsmc. I wouldn't expect anything for cheaper than $850-900 from Zen 5 if it's any good and leapfrog intel's refresh until arrow lake lands. this only works in amd's famous the sooner they get it out the door, otherwise we'll have a repeat of this present gen where they came out within weeks of each other due to delays by each company. zen 4 still sells more based on chart sales from what I guess estimate but am4 still outsells both.

 

[Saylick]

Very impressive shrink. Wonder what clocks would look like though.

I think it was in the low to mid-2 GHz range for Zen 4c.