Speculation: Ryzen 4000 series/Zen 3

[A///]

That would not have been possible, not with the specs we see today. And I don't think anyone would want to see PS5 with GF 12nm chips in it to be perfectly honest. As far as Zen3 and RDNA2 go, I agree that AMD shouldn't be taking this long, but they obviously want to sell through their current-gen products just a little longer.

Given AMD's language of desktop RDNA2 coming before consoles, I'd say there will be a major announcement in the next 45-60 days. I feel like consoles will be a November or December launch because parents will be more inclined to make it that one amazing gift for their children. Especially given how 2020 has played out. The psychology holds up.

 

[soresu]

Given AMD's language of desktop RDNA2 coming before consoles, I'd say there will be a major announcement in the next 45-60 days. I feel like consoles will be a November or December launch because parents will be more inclined to make it that one amazing gift for their children. Especially given how 2020 has played out. The psychology holds up.

Consoles have to be out by late october to early november or parents may not have enough time to either scrounge together the funds, or even procure them for christmas presents if/when they do have funds.

 

[Kedas]

How much would an I/O die in 7nm be different between DDR4 and DDR5.
If not much difference I think Zen3 may already have an 7nm I/O die, the APU has the 7nm I/O
I don't think it's a big issue to have the same die for DDR4 and DDR5 (obviously it can only do one when it is assembled/configured)

Advantage:
You don't have to make the I/O die again for DDR5 if you already keep DDR5 in mind.
Earlier/easier testing for AM5 platform. (all circuits not for DDR5 on the I/O die have already been tested)
Easily switch demand for DDR4 or DDR5 with the same die.
A bit less heat for Zen3 CPU
Both dies are produced by the same manufacturer. (cheaper/easier logistics)

Disadvantage:
Will take a little more die space with DDR5 support.
The die has to be ready earlier, for Zen3 launch. So it's a time gamble because if it's too late everything of Zen3 shifts in time.

So did they play safe just using the old die or take the risk....

 

[soresu]

How much would an I/O die in 7nm be different between DDR4 and DDR5.

Depends - the DDR5 spec calls for more circuitry on the DIMMs themselves but less board side, so this may be reflected in chip/package level IO too.

 

[Kedas]

Apparently it wouldn't be a first to combine DDR5 and DDR4 in one controller on tsmc 7nm:

DDR5/4 Controller IP | Synopsys

Synopsys secure DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standard DDR5 and DDR4 SDRAMs and DIMMS.

www.synopsys.com

DesignWare DDR5/4 PHY IP for TSMC 7-nm

Design And Reuse - From silicon cores platform, SoC solutions to IoT and AI

www.drgateway.com

 

[A///]

Consoles have to be out by late october to early november or parents may not have enough time to either scrounge together the funds, or even procure them for christmas presents if/when they do have funds.

Credit cards.

 

[soresu]

Credit cards.

Speak not of the evil one.

 

[soresu]

Apparently it wouldn't be a first to combine DDR5 and DDR4 in one controller on tsmc 7nm:

It would be nice if they pulled a Deneb/Phenom II, but I wouldn't count on it happening - especially as they were pretty final about the tail end of AM4 (DDR4) support in 2020.

On an unrelated IO tech note, interestingly I have seen news on the ether about a future NVMe 2.0 - though no idea when that lands.

It sounds as if they are making pains to divorce the NVMe standard from PCIe specific technology so that they can make it carrier agnostic - probably so that they can fold all the various new carrier specific variants back under a singular umbrella of NVMe.

I'm still waiting for them to design a more simplistic NVMe cable for consumers to replace regular SATA, because SATAe is both dead and based on an inferior protocol - and the U2 standard seems to be the SAS of NVMe.

Having a decent, simple NVMe cable would allow us to remove the toaster NVMe drives from the motherboard (and GPU proximity).

 

[jpiniero]

Consoles have to be out by late october to early november or parents may not have enough time to either scrounge together the funds, or even procure them for christmas presents if/when they do have funds.

Sony's last two consoles were released in the US on November 15th and 17th.
MS's last two consoles were released in the US on November 22nd (both times).

I think it'll be closer to Black Friday actually but I don't think you should rule out either being pushed out to next year.

 

[amrnuke]

Speak not of the evil one.

I abuse credit cards like crazy. 0% APR x 15-18 months is pure free money. I typically throw stuff on those cards and use the money I'd have spent on a MMA, CD ladder, or even a 13-15 month bond investment that pays out before the final bill is due on the credit card. Make a nice couple of percent cash just by opening a card. Even better if it's a cash back card and you can get 1-2% cash back on top of 0% APR.

I have an Amex Blue Cash Preferred. 6% back at grocery stores. Combined with Kroger's 4x gift cards and fuel perks, that 6% has been amazing - $250 in gift cards for stuff I'd purchase anyway = $1.00 off at the pump, my wife and I go together and save ~$25 minimum filling both tanks. That's 16% cash back. Even if you fill one 15 gallon car, it's still >10% cash back. Insane benefits. There's an annual fee that's dwarfed by the >$500 we saved using it on gift cards and fuel perks when combined with Kroger's rewards.

The point being that credit cards are like guns. Whether they're evil or not depends on the hand they're in.

 

[jamescox]

Good point. When they go to interposer design, then they can narrow the I/O pad pitch and shrink.

If they only make the IO die as an interposer, then they would need the same number of off die connections on the interposer. They could add more stuff, but the IO interposer might not be much smaller. Making the entire package as an interposer (cpu die and IO all on one interposer) seems like it would be huge. Current Epyc Rome is around 1000 square mm of silicon total, which is over the reticle limit. They can make interposers larger than the reticle limit, but it is probably significantly more expensive than a smaller interposer which can already be cost prohibitive.

They get a lot of advantages by being able to bin cpu chips for use in Ryzen desktop parts and Epyc parts. Going with cpu chiplets on an interposer may be too expensive for desktop parts, so they would lose that ability if they use an interposer cpu chiplet in Epyc but not Ryzen. They could move an 8 core APU up to cover more of the mainstream market and only have interposer based parts on the very high end. That doesn’t give them the same economy of scale though. It is unclear how AMD would make use of interposers for Epyc while still maintaining the the same level of modularity and design reuse. AMD has incredible modularity and design reuse with Zen 2. It isn’t just the cpu chips, the x570 chipset is the same design as the Ryzen IO die.

 

[DisEnchantment]

If they only make the IO die as an interposer, then they would need the same number of off die connections on the interposer. They could add more stuff, but the IO interposer might not be much smaller. Making the entire package as an interposer (cpu die and IO all on one interposer) seems like it would be huge. Current Epyc Rome is around 1000 square mm of silicon total, which is over the reticle limit. They can make interposers larger than the reticle limit, but it is probably significantly more expensive than a smaller interposer which can already be cost prohibitive.

They get a lot of advantages by being able to bin cpu chips for use in Ryzen desktop parts and Epyc parts. Going with cpu chiplets on an interposer may be too expensive for desktop parts, so they would lose that ability if they use an interposer cpu chiplet in Epyc but not Ryzen. They could move an 8 core APU up to cover more of the mainstream market and only have interposer based parts on the very high end. That doesn’t give them the same economy of scale though. It is unclear how AMD would make use of interposers for Epyc while still maintaining the the same level of modularity and design reuse. AMD has incredible modularity and design reuse with Zen 2. It isn’t just the cpu chips, the x570 chipset is the same design as the Ryzen IO die.

AMD has a patent which is trying to solve this problem. (see US10714462B2) The interposer is much smaller and only touches the chiplets partially.
The chiplets could have the microbumps on one section only, or they can use RDL to reroute in case there is a need to reuse chiplets where the microbumps are evenly distributed, but man this is a complex packaging.

 

[LightningZ71]

With the I/O die being an interposer, and if they keep at roughly the same size of socket and package that they currently use, they could use an intermediate, high efficiency node from TSMC, such as their 10nm, to produce the I/O die, then, there would be room enough on top of that I/O die for four 7nm/5nm chiplets. That would give them up to 32 cores on the AM5 socket. There's no need to go interposer on Epyc just yet. they have more than enough space on the existing package. If they went with a smaller node for the I/O die, they could shrink it a bit and fit a few more chiplets on the package. It also needs to gain some energy efficiency, which a smaller node can also help with.

 

[DisEnchantment]

With the I/O die being an interposer, and if they keep at roughly the same size of socket and package that they currently use, they could use an intermediate, high efficiency node from TSMC, such as their 10nm, to produce the I/O die, then, there would be room enough on top of that I/O die for four 7nm/5nm chiplets. That would give them up to 32 cores on the AM5 socket. There's no need to go interposer on Epyc just yet. they have more than enough space on the existing package. If they went with a smaller node for the I/O die, they could shrink it a bit and fit a few more chiplets on the package. It also needs to gain some energy efficiency, which a smaller node can also help with.

Zen3 would probably not have an interposer.
But I think Zen4 with X3D would definitely be interposer based. Connecting the memory stacks to the compute dies via IFOP would not be feasible.

 

[Gideon]

One way to keep the interposer size in check for Epyc would be to split into 4 identical (but rotated) parts and possiblt keeping the separate I/O die on top.

The I/O die would be in the middle of the SKU and evenly placed on top of all 4 interposers (essentially being divided into 4 quadrants as it is now) while the CPU chiplets would be entirely on ta single interposer (two chips per interposer).

The packaging would probably be even more complex than in the aforementioned patent though.

One benefit of it would be simpler thermal design, as it would avoid running all the i/o logic under CPU chiplets. It would waste a lot of r oom and silicon for the I/O die though, which could instead be used for more cores (with I/O underneath them)

 

[jamescox]

One way to keep the interposer size in check for Epyc would be to split into 4 identical (but rotated) parts and possiblt keeping the separate I/O die on top.

The I/O die would be in the middle of the SKU and evenly placed on top of all 4 interposers (essentially being divided into 4 quadrants as it is now) while the CPU chiplets would be entirely on ta single interposer (two chips per interposer).

The packaging would probably be even more complex than in the aforementioned patent though.

One benefit of it would be simpler thermal design, as it would avoid running all the i/o logic under CPU chiplets. It would waste a lot of r oom and silicon for the I/O die though, which could instead be used for more cores (with I/O underneath them)

The patent sounds similar to intel EMIB. Such packaging tech is expensive and somewhat risky. AMD is going to be very conservative with Epyc parts. They might be able to push things a bit more with HPC specific parts, but it would be a disaster to have some unreliable packaging for general server parts. I have been suspicious of the EMIB style design since you are kind up putting a chip with micro bumps that require super precise alignment across two different materials. Differing rates of expansion and contraction with thermal changes could be a more serious probleM compared to a full silicon interposer. Cpu chips don’t really seem to need to be on the interposer with how fast and power efficient infinity fabric seems to be.

edit: also, you would generally want the cpu chiplets to be stacked on top for cooling. With interposers, an active interposer would make the most sense since it would allow much smaller area. If they could put all of the larger transistors required to drive external interfaces in an active interposer and stack everything else on top, then they could shrink the size significantly. The chips would be slightly smaller since interposer interconnect takes a lot less die area compared to serdes links. that wouldn’t be for Zen 3 and possibly not even for Zen 4 though.

 

[eek2121]

Consoles have to be out by late october to early november or parents may not have enough time to either scrounge together the funds, or even procure them for christmas presents if/when they do have funds.

The date I've heard is November 18th.

 

[soresu]

The date I've heard is November 18th.

Close enough, or it would be in any other year - this year somewhat less so as I'm afraid a great many parents may have other financial considerations weighing upon them.

 

[A///]

If you're basing release data on a pandemic and economic recession, then Sony and Microsoft would be better off delaying their console launches for the next 2-3 years as the economy beings to recover provided there's a vaccine out by then.

The show must go on, Monsieur/Madame Soresu.

 

[Markfw]

If you're basing release data on a pandemic and economic recession, then Sony and Microsoft would be better off delaying their console launches for the next 2-3 years as the economy beings to recover provided there's a vaccine out by then.

The show must go on, Monsieur/Madame Soresu.

The vaccine is in phase 3 testing. Just Kaiser Permanente alone just gave it to 30,000 people.

It should be widely available by the fall.

 

[A///]

The vaccine is in phase 3 testing. Just Kaiser Permanente alone just gave it to 30,000 people.

It should be widely available by the fall.

Which vaccine?

 

[Ajay]

The vaccine is in phase 3 testing. Just Kaiser Permanente alone just gave it to 30,000 people.

It should be widely available by the fall.

True, but there's no way it will be 'widely available' by fall. Six months, maybe, if the results and safety are very good to excellent. Vaccine in question is mRNA-1273 by Moderna - but this is really stuff for another thread.

 

[Markfw]

True, but there's no way it will be 'widely available' by fall. Six months, maybe, if the results and safety are very good to excellent. Vaccine in question is mRNA-1273 by Moderna - but this is really stuff for another thread.

Yes, sorry I was just replying to his comment about it being years out. We should drop this now to stay on topic, agreed.

 

[amrnuke]

Still quite amazed at how few leaks we have on Zen3 desktop. This is incredible NDA enforcement by AMD if there's no delay...

 

[soresu]

Still quite amazed at how few leaks we have on Zen3 desktop. This is incredible NDA enforcement by AMD if there's no delay...

Far weirder because at this point we had way more info about Zen and Zen2 relative to their release date.

While we have basically zip about Zen3 beyond the unified L3 CCD.