- Apr 21, 2017
I'm considering the simpler case here of a single 8c/16t CCD AM4 chip. Consider a single thread running on this.That's not how it works.
In Zen2 case we have a 2x16MB L3, in Zen3 we have a unified 1x32MB L3.
Assume the thread does not jump between CCX's (if applicable).
Now in Zen2 case the thread is limited to filling up to one of the 16MB L3 units.
In Zen3 case we have the thread limited to filling a 32MB L3 cache.
This means potentially significantly greater hit rate (though at the supposed cost of almost 20% latency hit).