- Mar 3, 2017
I think perhaps for Zen3 it could remain the same. But I am just thinking from the context of the EHP where most AMD's patents indicated a Network on chip architecture using crossbars. in such scenarios it would makes sense. But this is all speculation anyway based on patents and public papers by AMD which though not totally baseless, may or may not find its may into a real product.But wouldn't tag directory in L3 be pretty useless? In memory controller directory check can be done in side of memory access - how would that be practical when directory and memory controller are in different dies? And instead of one directory there would be as many as chiplets so coherence traffic between chiplets would be many times more than with IOD.
But looking at the X3D it does seem like the EHP for which a good part of it is funded by the Fast Forward 2 program of the US DoE.