Speculation: Ryzen 4000 series/Zen 3

[Exist50]

I'm the only one who was telling SMT4 might be part of Zen3 since leaked it's new 19h family and it's completelly new uarch (Norrod from AMD). Me and Nosta was telling that Zen1 & Zen2 is just hybrid of Apple's A7 Cyclone and BD as a temporary survival CPU mixture done by Keller (who came from Apple). And that Zen3 is Keller's finally finished Alpha EV8 with SMT4 (Keller is ex-DEC/Alpha engineer) and developed in parallel with Zen2. Maybe you should read entire thread first.

If you think any part of that makes sense, you're demonstrating precisely why people are getting annoyed. As pointed out several times now, AMD confirmed Zen 3 to be 2 threads per core, period. There is no room for debate.

And do you seriously think the comparison to Nosta does you any favors? If anything, you should consider that a massive red flag.

 

[soresu]

AMD's general trend for the Zen-lineage is the smaller core that improves IPC and EPI is preferred over going bigger >6-wide, SMT4/SMT8, longer SIMDs(512-bit units/256-bit units) which isn't preferred.

Zen2 literally contradicts this statement, it is the first major change from Zen1 and doubles the SIMD units - this is the only trend we have witnessed thus far.

 

[soresu]

Edit: Misread the image.

 

[soresu]

And that Zen3 is Keller's finally finished Alpha EV8 with SMT4

Alpha EV8 was 8 wide.

The likelihood of AMD going 8 wide seems extremely small, especially with minimal process gains to swallow the power/area increase necessary for such a change.

 

[Thunder 57]

Who will eat cat food now about SMT4? Where is @Thunder 57 with all those strong words? He suddenly disappeared. Perhaps he went to Wallmart to buy some cat food cans....

I told you that SMT4 is on their technology map and it's just a matter of time which core will bring it. And server grade Zen3 with its completely new uarch is god damn good opportunity. And Golden Cove too to be honest.

Not just yet. First of all why is Genoa suddenly Zen 3? And suddenly Milan is 7nm+? I don't buy it.

 

[trexfromouterspace]

Not just yet. First of all why is Genoa suddenly Zen 3? And suddenly Milan is 7nm+? I don't buy it.

It's not and it's not.

 

[soresu]

Not just yet. First of all why is Genoa suddenly Zen 3? And suddenly Milan is 7nm+? I don't buy it.

That slide says 4Q18, something fishy this way comes.....

 

[uzzi38]

Why is Milan being 7nm+ suddenly a surprise?

There was a naming change a while back for 7nm. N7P and N7+ are now just called 7nm as well now, no more 7nm+ notation for anyone.

But this roadmap is before that change.

 

[Richie Rich]

Alpha EV8 was 8 wide.

The likelihood of AMD going 8 wide seems extremely small, especially with minimal process gains to swallow the power/area increase necessary for such a change.

Zen2 has .................11-wide back end,
Sunny Cove has ......10-wide back end,
Cortex X1 has .........15-wide back end.

8-wide EV8 was a monster back in 2000 but now it's a bit outdated in terms of width IMO.

 

[soresu]

Zen2 has .................11-wide back end,
Sunny Cove has ......10-wide back end,
Cortex X1 has .........15-wide back end.

8-wide EV8 was a monster back in 2000 but now it's a bit outdated in terms of width IMO.

It feels like every time I mention that something is n wide, some smart alec pulls a rabbit out of a hat.

X1 is 5 wide, as Zen2 is 4 wide, which is the number you know I was getting at.

 

[Richie Rich]

It feels like every time I mention that something is n wide, some smart alec pulls a rabbit out of a hat.

X1 is 5 wide, as Zen2 is 4 wide, which is the number you know I was getting at.

Every stage of CPU has different width. There is no such a thing like one single width number describing whole CPU and it's performance. BTW comparing decode width of CISC Zen2 and RISC Alpha EV8 is pure non-sense. The main and heavy work is done by execution units in back end. Not perfect but probably the best metric for cross-ISA comparison.

 

[NostaSeronx]

X1 is 5 wide, as Zen2 is 4 wide, which is the number you know I was getting at.

EV8 would be in richie's numbers 8+4+4 (8 Integer ALUs, 4 Floating ALUs, 2 Load+2 Store Units) => 16-wide.

 

[Richie Rich]

EV8 would be in richie's numbers 8+4+4 (8 Integer ALUs, 4 Floating ALUs, 2 Load+2 Store Units) => 16-wide.
View attachment 24486

Beautiful catch Nosta! Where did you found that? I searched for EV8 detais many times l but I never get any number of ALUs or anything in back-end.

8xALU, 4xAGU, 4xFPU and SMT4 on top of that back in 2001? You have to be kidding me!!! Too bad it was canceled.

I guess Zen3 is gonna be EV8-like core otherwise Keller wouldn't bother to move from Apple's 6xALU development. But maybe they cancelled that along with K12 for something less crazy and more 4xALUisch.

 

[quikah]

That slide says 4Q18, something fishy this way comes.....

It is not necessarily fishy, but it is old. Pretty pointless to speculate based on such old information. Things change, already several have been confirmed (Genoa is not Zen3).

 

[Mopetar]

If AMD ever did go SMT3/4 do you think Intel would decide go SMT5 in response?

 

[Thibsie]

Beautiful catch Nosta! Where did you found that? I searched for EV8 detais many times l but I never get any number of ALUs or anything in back-end.

8xALU, 4xAGU, 4xFPU and SMT4 on top of that back in 2001? You have to be kidding me!!! Too bad it was canceled.

I guess Zen3 is gonna be EV8-like core otherwise Keller wouldn't bother to move from Apple's 6xALU development. But maybe they cancelled that along with K12 for something less crazy and more 4xALUisch.

So you were indeed pulling numbers out of bottom.

 

[soresu]

Beautiful catch Nosta! Where did you found that? I searched for EV8 detais many times l but I never get any number of ALUs or anything in back-end.

8xALU, 4xAGU, 4xFPU and SMT4 on top of that back in 2001? You have to be kidding me!!! Too bad it was canceled.

I guess Zen3 is gonna be EV8-like core otherwise Keller wouldn't bother to move from Apple's 6xALU development. But maybe they cancelled that along with K12 for something less crazy and more 4xALUisch.

Try looking up the actual info on it, took me 30 seconds on Google and a bit longer reading.

When you look at the expected power increase from EV6/7 you can easily believe the ALU increases involved for that now ancient (but likely still used) node.

Again Keller and K12 is a non issue - he left when the main work on Zen was done with fine tuning being the last leg of the race to final stepping tape out.

Especially when you consider how cash strapped the R&D division was at that point, it simply was not tenable to cater for 2 separate CPU ISA uArch's at once while also dealing with console GPU custom development for 2 customers and their own desktop GPU uArch's all at the same time (not to mention Subor APU).

Something had to give, both time and funding demanded it - and x86 was the focus, it had to be.

If they had 2 to 3 times the R&D budget it might be a different story, but even if K12 had been finished, it may well have been canned afterwards as Qualcomm's server efforts were around the same time frame - back then ARM server was simply not taking off as it is now, and software was also still not there either, meanwhile many linux distros have since gone ARM.

Some people just don't stick around for any decades long period because they like variance in their job - albeit it seems Keller wasn't so fond of the work environment at Intel this time around.

Others have left AMD with a far murkier fanfare in the last decade, like Koduri and Gustafson for instance.

Gustafson had some interesting ideas for new compute math, but his short tenure implies this was not fated to be AMD's direction.

 

[soresu]

If AMD ever did go SMT3/4 do you think Intel would decide go SMT5 in response?

I feel like I need some Sheldon Cooper sarcasm gif to respond to this....

 

[Gideon]

Multiple leaks circulating in twitter about desktop Renoir higher FCLK support (2166 Mhz!):

https://twitter.com/x/status/1277766440494325760

If this is accurate, then Zen3 should be a very nice improvement in games because both due-to unified cache and much lower memory latency (though it would probably be ~5ns worse due to chiplets). With this rate, even Renoir might end up being faster than Matisse in some games with 4400 Mhz+ memory

Even though this is with an extremely impressive memory kit (4333 CL14) and might not be 100% stable, this is still a huge gain. Matisse reaaaally struggles to go below 60ns, even with similar crazy ram-kits and custom timings. Reasonable everyday OC with good-bang-for-buck memory is around 65-70ns even with custom timings.

This is about the best one can resonably hope for 24/7 config on Matisse (62.1 ns) and not every CPU can do 1900 FCLK (mine refuses to go above 1800 for instance)

Spoiler: Full image

EDIT:
And a video (by the original leaker) proving, it's not fake:

https://www.bilibili.com/video/BV1QT4y1J73T

 

[DrMrLordX]

@Gideon

If Renoir can hit fclk speeds that high, I'm thinking Matisse refresh might do it as well. Could be wrong though.

 

[Gideon]

@Gideon

If Renoir can hit fclk speeds that high, I'm thinking Matisse refresh might do it as well. Could be wrong though.

This is what u1smus hinted at as well (at least FCLK of 2000). We'll see. I do hope it's true though, should improve the "gaming IPC" by a noticable amount.

As for Zen 3 hopefully it scales even higher. After all, DDR5 starts with 4800 Mhz (similar to DDR4 2133 MHz) so they need to support much higher frequencies anyway, sooner, rather than later (as leaks seem to mention Zen3 APUs with DDR5 down the line).

 

[DrMrLordX]

After all, DDR5 starts with 4800 Mhz (similar to DDR4 2133 MHz) so they need to support much higher frequencies anyway, sooner, rather than later (as leaks seem to mention Zen3 APUs with DDR5 down the line).

Either that or they'll use different ratios instead of 1:1 where possible.

 

[Richie Rich]

Try looking up the actual info on it, took me 30 seconds on Google and a bit longer reading.

When you look at the expected power increase from EV6/7 you can easily believe the ALU increases involved for that now ancient (but likely still used) node.

Again Keller and K12 is a non issue - he left when the main work on Zen was done with fine tuning being the last leg of the race to final stepping tape out.

Especially when you consider how cash strapped the R&D division was at that point, it simply was not tenable to cater for 2 separate CPU ISA uArch's at once while also dealing with console GPU custom development for 2 customers and their own desktop GPU uArch's all at the same time (not to mention Subor APU).

Something had to give, both time and funding demanded it - and x86 was the focus, it had to be.

If they had 2 to 3 times the R&D budget it might be a different story, but even if K12 had been finished, it may well have been canned afterwards as Qualcomm's server efforts were around the same time frame - back then ARM server was simply not taking off as it is now, and software was also still not there either, meanwhile many linux distros have since gone ARM.

Some people just don't stick around for any decades long period because they like variance in their job - albeit it seems Keller wasn't so fond of the work environment at Intel this time around.

Others have left AMD with a far murkier fanfare in the last decade, like Koduri and Gustafson for instance.

Gustafson had some interesting ideas for new compute math, but his short tenure implies this was not fated to be AMD's direction.

I'm afraid you have no clue what you are talking about. AMD had big debts which is paying till these days. AMD's resurrection was done thanks to big bank loans. That's how the big business works. There is no problem to spend twice as much for R&D when you target is set to return to the TOP (this will pay back 10x times more). Look how much Softbank is burning money in ARM LLC. Is it worth? Definitely, because they invades server market big way. So stopping ambitious server ARM K12 project in 2015 (year when A77 and server Neoverse N1 development started) is very bad move. In 2016 Softbank bought ARM Holding and started burn huge money there (resulting in two big cores a year A78/X1 released this year). And also Fujitsu A64FX development started around 2015 including SVE vectors. To cancel K12 during this huge ARM movement was very bad idea.

And regarding the 6xALU. If Zen3 is the Keller's resurrected EV8 with 8xALUs and SMT4 let's see how many naysayers will keep saying ALU number doesn't matter still. I guess as usual it will start matter since their favorite brand adopts that missing feature

 

[Makaveli]

Multiple leaks circulating in twitter about desktop Renoir higher FCLK support (2166 Mhz!):

https://twitter.com/x/status/1277766440494325760

If this is accurate, then Zen3 should be a very nice improvement in games because both due-to unified cache and much lower memory latency (though it would probably be ~5ns worse due to chiplets). With this rate, even Renoir might end up being faster than Matisse in some games with 4400 Mhz+ memory

Even though this is with an extremely impressive memory kit (4333 CL14) and might not be 100% stable, this is still a huge gain. Matisse reaaaally struggles to go below 60ns, even with similar crazy ram-kits and custom timings. Reasonable everyday OC with good-bang-for-buck memory is around 65-70ns even with custom timings.

This is about the best one can resonably hope for 24/7 config on Matisse (62.1 ns) and not every CPU can do 1900 FCLK (mine refuses to go above 1800 for instance)

Spoiler: Full image

EDIT:
And a video (by the original leaker) proving, it's not fake:

https://www.bilibili.com/video/BV1QT4y1J73T

That looks great I think even if we get a FCLK of 2000 with DDR4000 on Zen 3 that alone will provide a hugh boost.

 

[cortexa99]

Looks like 49ns which leaked few days ago is true data not a bug(see Renoir dedicated thread). His memory kits win silicon lottery to get this result. Yeah it's same guy.