Speculation: Ryzen 4000 series/Zen 3

[maddie]

That's where I stand as well. No way AMD is moving an N7+ design to N5P (which don't use the same design rules) on such a short notice, with the former already being used for sampling in datacenters. TSMC is accelerating mass production N5P, so may have asked AMD to do the same for its silicon design already in the work for N5P which would be Zen 4, not 3. Though AMD's first N5P design actually realistically would be a GPU pipecleaner. This report doesn't amount to much imo.

I really can't see Zen4 being able to be pulled in so quickly, whereas migrating Zen3 from 7EUV to 5Euv should be a lot easier and quicker. As I posted earlier, there's no rule preventing Zen3 on both 7nm and 5nm. One for server (7nm) and the other for desktop (5nm). I know everyone thinks that it must be the other way, but I see a good reason for it this way. The I/O die design is common to all in any case. Isn't this one of the benefits of a chiplet design. Should AMD religiously follow the stated roadmap, even in the face of quicker advancement?

Anyone can estimate the time needed to migrate a synthesizable design to a different node using the same RTL file? Isn't this exactly what AMD has worked so hard to exploit in order to be agile?

 

[DisEnchantment]

Anyone can estimate the time needed to migrate a synthesizable design to a different node using the same RTL file? Isn't this exactly what AMD has worked so hard to exploit in order to be agile?

From RTL is still too high level. So many steps still involved.
Physical design, layout, place and route, signal integrity, clock domains, power planes etc behave differently on different processes due to difference of the electrical characteristics of the different layers. High frequency designs are even more affected by these.
~8-10 months is being extremely optimistic.
That said you can buy ready made libraries from Synopsys or someone for that particular process and speed up things. But there are things which are your own stuffs like cores, power design and stuff which you need to redo.

 

[maddie]

From RTL is still too high level. So many steps still involved.
Physical design, layout, place and route, signal integrity, clock domains, power planes etc behave differently on different processes due to difference of the electrical characteristics of the different layers. High frequency designs are even more affected by these.
~8-10 months is being extremely optimistic.
That said you can buy ready made libraries from Synopsys or someone for that particular process and speed up things. But there are things which are your own stuffs like cores, power design and stuff which you need to redo.

Taking 12 months as possible with some dedicated work, would mean that they needed to start last Dec or Jan for a late 2020 release. The whole extreme secrecy about Zen3 tells me something is afoot. 3-5 months before a possible release and no leaks. Surely MB manufacturers would have had access to early models already. True?

 

[moinmoin]

Taking 12 months as possible with some dedicated work, would mean that they needed to start last Dec or Jan for a late 2020 release. The whole extreme secrecy about Zen3 tells me something is afoot. 3-5 months before a possible release and no leaks. Surely MB manufacturers would have had access to early models already. True?

The port would need to be finished before a tape out. And tape outs usually happen a little less than a year before volume production. Samples are created from that point on.

 

[DisEnchantment]

Taking 12 months as possible with some dedicated work, would mean that they needed to start last Dec or Jan for a late 2020 release. The whole extreme secrecy about Zen3 tells me something is afoot. 3-5 months before a possible release and no leaks. Surely MB manufacturers would have had access to early models already. True?

They need to have started migrating to the N5 PDK beforehand. PDK is available even before process is ready. From there they do tape out. After tapeout they optimize the physical design, layout, routing and such. TSMC provides cloud based infrastructure to simulate this and they are doing a lot to speed this up so that porting designs to new PDK is faster.

ARM SoCs are typically faster in migrating.
But high frequency x86 are more challenging because of signal integrity, clocks, propagation delays, races and so on
I read somewhere it is faster to migrate GPUs to new nodes.

Also verification of x86 chips is a lot complex.

 

[LightningZ71]

TSMC N5 isn't exactly brand spanking new. Apple has been producing volume on it for a while now. N5P is supposedly just a refinement of it, and was planned for over a year ago. So, this isn't some mystery node that just appeared out of thin air.

I contend that AMD has learned it's lesson from past troubles with being beholden to a single upcoming foundary node and, now that they actually have a decent revenue stream, have been hedging their bets by designing for multiple target nodes. We also know that TSMC has been helping their customers with this process to increase their foundary utilization numbers and to get quicker ROI as well as to guard against customers leaving for Samsung. It is not impossible that AMD and TSMC have worked together to get ZEN 3 ready on both N7(improved) and N5P.

 

[uzzi38]

I can't even keep up with the leaks...

AMD Ryzen 5000 Zen3 “Warhol” to succeed Vermeer

AMD Ryzen 5000 Zen3 "Warhol" to succeed Vermeer? - VideoCardz.com

A new leak appears to indicate that Zen3 Desktop architecture will be codenamed “Warhol”. AMD Warhol Posted by @MebiuW on Twitter (now deleted), the picture appears to be from some kind of an internal roadmap. It not only mentions “Warhol”, so far an unknown codename, but also two letters from a...

videocardz.com

This one is BS.

The poster of that rumour is trying to push that Zen 4 and AMD using 5nm for the first time is Q2-Q3 2022, which is completely and utterly wrong. Ignore anything he says.

 

[moinmoin]

TSMC N5 isn't exactly brand spanking new.

April 2020 volume production is very sparkly though.

It is not impossible that AMD and TSMC have worked together to get ZEN 3 ready on both N7(improved) and N5P.

True, I thought the details of AMD adaption to N7 showed they should have a close working relationship indeed.

Though it warrants to remember that the whole process in getting chips to be created on those finer nodes is the most expensive part of producing chips nowadays. So with AMD's greediness wrt the number of different die designs I find it hard to believe they pay for the whole upfront process cost without any intention to making use of it. That's why I don't think they'd have the same design on incompatible different nodes.

 

[Ajay]

They need to have started migrating to the N5 PDK beforehand. PDK is available even before process is ready. From there they do tape out. After tapeout they optimize the physical design, layout, routing and such. TSMC provides cloud based infrastructure to simulate this and they are doing a lot to speed this up so that porting designs to new PDK is faster.

Tapeout, IIRC, is for creating the masks and, I assume, process steps (etch, poly, metal, etc.).

 

[JasonLD]

Zen 3 is already expected to be decent improvement over Zen 2 on improved N7. I don't see why AMD has to alter that plan and accelerate to 5nm while sacrificing margin and yield they would get from 7nm. It would make sense if Intel pulls a surprise move to 7nm next year but chance of that happening is close to zero.

 

[maddie]

Zen 3 is already expected to be decent improvement over Zen 2 on improved N7. I don't see why AMD has to alter that plan and accelerate to 5nm while sacrificing margin and yield they would get from 7nm. It would make sense if Intel pulls a surprise move to 7nm next year but chance of that happening is close to zero.

There is a battle for leading edge wafers ongoing. Why is this ignored. Does anyone think AMD or any other company could just decide arbitrarily on when they alone need a certain product and not account for others snapping up future production? Use it or lose it appears to be the game with TSMC at present as they are the clear fab leader. This has to be factored in whatever changes might have been made to roadmaps.

 

[JasonLD]

There is a battle for leading edge wafers ongoing. Why is this ignored. Does anyone think AMD or any other company could just decide arbitrarily on when they alone need a certain product and not account for others snapping up future production? Use it or lose it appears to be the game with TSMC at present as they are the clear fab leader. This has to be factored in whatever changes might have been made to roadmaps.

At what cost? It doesn't make a business sense to alter what is already a solid roadmap just to get on board with leading edge node asap while giving up on proven node with great yield, margin, and volume.

 

[maddie]

At what cost? It doesn't make a business sense to alter what is already a solid roadmap just to get on board with leading edge node asap while giving up on proven node with great yield, margin, and volume.

Not to get on board ASAP by itself, but if you don't get on board when offered you might have to wait longer than expected for when production scales up. Others will have taken your position. Do you expect TSMC to keep production capacity idle while AMD or anybody decides when is the right time to advance? They sell capacity as soon as possible and it's up to their customers to reserve volume. As I said, use it or lose it.

TSMC right now can be seen as kingmakers.

 

[itsmydamnation]

The thing to remember is amd x86 doesn't complete with any other TSMC customers for end sales. So from a revenue growth from TSMC perspective, getting amd to buy big wafers on new process is massive growth. TSMC can always build more fabs.

Now the questions are, how early did TSMC think 5nm was a homerun / working great. How early/did AMD/TMSC talk about accelerating to 5nm. What products does that line up to.

 

[lightmanek]

The thing to remember is amd x86 doesn't complete with any other TSMC customers for end sales. So from a revenue growth from TSMC perspective, getting amd to buy big wafers on new process is massive growth. TSMC can always build more fabs.

Now the questions are, how early did TSMC think 5nm was a homerun / working great. How early/did AMD/TMSC talk about accelerating to 5nm. What products does that line up to.

I remember our NostaSeronox telling everyone that TSMC gave AMD an offer to accelerate 5nm adoption or be left behind a long time ago. I vaguely remember it was around Zen2 launch, so this would give enough time to realign some of the plans.
When I'm not on the phone, I might try to find that post, or maybe poster himself can tune in and refresh our memories.

 

[NTMBK]

I remember our NostaSeronox telling everyone that TSMC gave AMD an offer to accelerate 5nm adoption or be left behind a long time ago. I vaguely remember it was around Zen2 launch, so this would give enough time to realign some of the plans.
When I'm not on the phone, I might try to find that post, or maybe poster himself can tune in and refresh our memories.

Holy crap, you're right!

Hot and spicy rumor, get out your table salt.

AMD has canned all 7nm+(7nm EUV) projects that are APU/CPU/GPU 2.5D/3D. AMD instead will be launching them on the 5nm node at the soonest.

7nm DUV, 7nmP DUV, 5nm EUV is the new timeline from an unnamed individual from TW.

Stuff to watch out for: RRD. Three new CCDs at TSMC. Of which one is for the new Renoir(7nm) and its successor Rembrandt(5nm). The D one is for a semi-custom project on 6nm(not AMD mainline, however it might get pushed to 5nm).

TSMC doesn't like the 7nm/7nm+ as first customer, so they want AMD to be on 5nm.

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[Valantar]

Holy crap, you're right!

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Interesting, though there's a rather glaring factual error there: calling Renoir a CCD. Monolithic dice are not CCDs, so something there doesn't add up. Of course that might just mean that the entire "RRD" thing is monolithic chips and not CCDs.

 

[jpiniero]

There's also the frontier cpu for the DOE:
AMD Confirms Zen 4 EPYC Codename, and Elaborates on Frontier Supercomputer CPU
Forrest explained that the CPU is not Milan – it is actually a fully custom design CPU specifically for this project.

I was going to say that if they were going to release anything 5 nm that soon, it would be HPC related. I suppose it could include a CPU too that could be repurposed for desktops at some point. The timing doesn't match up for me for for it to directly replace releasing Vermeer though.

 

[uzzi38]

Holy crap, you're right!

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Yeah, this rumour is one of the things that makes me think that N5P is actually for Rembrandt first, not for Vermeer/Milan. The guy's LinkedIn profile did pretty clearly say he was working with 5/6/7nm and had worked on Renoir/Durango/Rembrandt in no particular order.

However, there is one more rumour to discuss regarding all of this.

Re: [閒聊] ZEN3 改用5nm+？

以我目前看到的 我覺得改製程是真的 但不會直接5nm 1. N21/22 tape out都還是7nm 最近的N23就改惹 可是這樣就變成老大老二用舊的，老么用新的?

www.ptt.cc

The poster here is apparently saying there wasn't a retape to N5P but instead to N6. It's uh, still extremely unlikely to say the least... but this guy did leak the RDNA2 die sizes, and the size for Navi21 that he talked about I am pretty confident is accurate at least, so it's hard to ignore what he's written.

 

[jpiniero]

I thought Vermeer was intended to be 7+... 6 wouldn't make sense. The timing would be correct I think, Q1 21 is when 6 is supposed to be first available.

 

[uzzi38]

I thought Vermeer was intended to be 7+... 6 wouldn't make sense.

You're right, it doesn't. I agree actually. N7+ isn't IP compatible with N6... N7P is though. I did post the rumour, but by no means did I think what he said about Vermeer/Milan was likely.

I wouldn't be surprised if he's right about Navi23, but I can't see it happening for Zen 3 based products.

 

[NostaSeronx]

N6 wasn't IP-compatible in 2019, but it should eventually be IP-compatible. TSMC 7nm DUV can move to 6nm EUV(Cx=Mx) and 7nm EUV can move to 6nm EUV(2/3Cx=Mx). Everything is planned to be pushed towards 6nm as the long-term node. As it upports some of the EUV tweaks from 5nm for the 7nm nodes.

AMD's 7nm at TSMC isn't a custom-grade node(like: GF28SHP/GF28A/GFFinFET-Boost+) but the 5nm that AMD will be using is a custom-grade node. So, while 7nm AMD is exactly 1:1 with the TSMC perf/power, 5nm TSMC with AMD might have more performance/power than published by TSMC for N5.

Altered LG/MG/SG/EG stuff => 0.5V->0.6V/0.75V->0.85V/1V->1.1V/1.2V->1.25V/1.5V->1.55V/1.8V->2.1V etc
Increased SiGe/Spacer/Vt tweaks per year(N5A -> N5A+ -> N5A++, A standing for AMD) => 2020(baseline) -> 2021(5% improvement) -> 2022(7.5% improvement), etc
(Hisilicon is supposedly in an agreement to re-use AMD's tweaks, with them making custom-level standard cells for AMD)

 

[LightningZ71]

Well, Nosta's prognostications and leaks do relatively match up, though with the expected minor wording quibbles such leaks bring. We know that AMD has announced that Zen3 wasn't going on N7P, and was even cagey about it being on N7+, just noting that it was an "improved 7nm node". Renoir was too far along on N7 to change anything. This rumor of Zen3 being also on 5nm matches with TSMC desiring AMD to be on N5/N5P. IT also follows that at least some Zen3 CCDs will be made on improved N7 as the next EPYC parts have been in validation for some time. So, it shakes out like this:

Zen3: impN7 CCDs for Epyc and low end Ryzen. N5P CCDs for High end Ryzen and maybe Threadripper. A pair of APUs, one with VEGA and one with RDNA.
Zen4: It's reasonable to suspect that it will be on an improved N5P process unless N3 is drastically quicker than expected.

 

[DisEnchantment]

My previous theory has always been N7P, but now with everything leaking around like no tomorrow I am not sure.
My thinking was that

• The whole narrative about IOD not scaling at all while not untrue does not paint the complete picture. Renoir is proof of this. And TSMC's numbers also indicate the density gains for PHYs, analog blocks etc to be around 20-30% which are far less than the 80% gain in SRAM density but tangible nonetheless(vs previous node). They could make the IOD on N7
• Using everything TSMC, including IOD, is probably better, in that logistics are going to be slightly better, everything is fabbed at TSMC.
• A smaller IOD would leave lots of wiggle room for core and cache design. This means HP cell libraries could be feasible, for desktop at least, since the CCDs can be a bit bigger.
• If Renoir is anything to go by, a density gain of 20% over Zen2 CCD is guaranteed. There was no real frequency regression.
• Will server CCDs be same as desktop CCDs. Or will there be two sets of HP(Lower density performance oriented) and HD (Higher density efficiency oriented) CCDs, or will the Zen3 CCDs be same at all.

If Zen2 HD libs can hit 4.4 GHz, the HP cells would definitely hit 4.8+ (TSMC's own estimates). Add to that increased die area available from a potential usage of TSMC IOD. There would be room for larger caches and wider cores.

Will the WSA get in the way of innovation. Will the Zen3 designs use anything from GF at all? Lisa mentioned yesterday that Rome will be very much in production next year as well, add to that, the Pro and embedded series, there is a good chance they could meet these WSA obligations without constraining Zen3 chiplet designs by sticking with GF.

Of course Mobile is a different game, and it would make sense to move to N5(P)

 

[moinmoin]

There is a battle for leading edge wafers ongoing. Why is this ignored.

Because AMD so far wasn't a participant in any battle for leading edge wafers. They picked up/for consoles are still picking up 7nm when leading edge customers moved on to 5nm already.

Not to get on board ASAP by itself, but if you don't get on board when offered you might have to wait longer than expected for when production scales up. Others will have taken your position. Do you expect TSMC to keep production capacity idle while AMD or anybody decides when is the right time to advance? They sell capacity as soon as possible and it's up to their customers to reserve volume. As I said, use it or lose it.

TSMC right now can be seen as kingmakers.

You are creating some urgency where there is none. The lead time of around half a year for wafer orders is well known by now, and AMD is not waiting until the last second to make such orders.

I think AMD's modus operandi is pretty clear to see: They are involved with the leading edge nodes from the start, but the time isn't used for actual volume production, some GPU pipecleaners aside, but instead for adapting and optimizing the die for the node, to a point that AMD is reluctant mentioning TSMC's node names and rumors are now talking about optimizations being AMD specific and other TSMC customers wanting a part of it as well.

Now the questions are, how early did TSMC think 5nm was a homerun / working great. How early/did AMD/TMSC talk about accelerating to 5nm. What products does that line up to.

As pointed out before we should consider there to be a 1-2 years lead time minimum for a new/ported design on a new node. This means AMD was confronted with the decision of adopting 5nm early around 2 years ago. I don't think AMD back then would have been willing (even able?) to double its work on Zen 3 just to add a potentially redundant node. The logical choice back then would be accelerating what was already destined to be in the making for 5nm, and that's Zen 4.