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Speculation: Ryzen 4000 series/Zen 3

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LightningZ71

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Well, Nosta's prognostications and leaks do relatively match up, though with the expected minor wording quibbles such leaks bring. We know that AMD has announced that Zen3 wasn't going on N7P, and was even cagey about it being on N7+, just noting that it was an "improved 7nm node". Renoir was too far along on N7 to change anything. This rumor of Zen3 being also on 5nm matches with TSMC desiring AMD to be on N5/N5P. IT also follows that at least some Zen3 CCDs will be made on improved N7 as the next EPYC parts have been in validation for some time. So, it shakes out like this:

Zen3: impN7 CCDs for Epyc and low end Ryzen. N5P CCDs for High end Ryzen and maybe Threadripper. A pair of APUs, one with VEGA and one with RDNA.
Zen4: It's reasonable to suspect that it will be on an improved N5P process unless N3 is drastically quicker than expected.
 
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DisEnchantment

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My previous theory has always been N7P, but now with everything leaking around like no tomorrow I am not sure.
My thinking was that
  • The whole narrative about IOD not scaling at all while not untrue does not paint the complete picture. Renoir is proof of this. And TSMC's numbers also indicate the density gains for PHYs, analog blocks etc to be around 20-30% which are far less than the 80% gain in SRAM density but tangible nonetheless(vs previous node). They could make the IOD on N7
  • Using everything TSMC, including IOD, is probably better, in that logistics are going to be slightly better, everything is fabbed at TSMC.
  • A smaller IOD would leave lots of wiggle room for core and cache design. This means HP cell libraries could be feasible, for desktop at least, since the CCDs can be a bit bigger.
  • If Renoir is anything to go by, a density gain of 20% over Zen2 CCD is guaranteed. There was no real frequency regression.
  • Will server CCDs be same as desktop CCDs. Or will there be two sets of HP(Lower density performance oriented) and HD (Higher density efficiency oriented) CCDs, or will the Zen3 CCDs be same at all.
If Zen2 HD libs can hit 4.4 GHz, the HP cells would definitely hit 4.8+ (TSMC's own estimates). Add to that increased die area available from a potential usage of TSMC IOD. There would be room for larger caches and wider cores.

Will the WSA get in the way of innovation. Will the Zen3 designs use anything from GF at all? Lisa mentioned yesterday that Rome will be very much in production next year as well, add to that, the Pro and embedded series, there is a good chance they could meet these WSA obligations without constraining Zen3 chiplet designs by sticking with GF.

Of course Mobile is a different game, and it would make sense to move to N5(P)
 

moinmoin

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There is a battle for leading edge wafers ongoing. Why is this ignored.
Because AMD so far wasn't a participant in any battle for leading edge wafers. They picked up/for consoles are still picking up 7nm when leading edge customers moved on to 5nm already.

Not to get on board ASAP by itself, but if you don't get on board when offered you might have to wait longer than expected for when production scales up. Others will have taken your position. Do you expect TSMC to keep production capacity idle while AMD or anybody decides when is the right time to advance? They sell capacity as soon as possible and it's up to their customers to reserve volume. As I said, use it or lose it.

TSMC right now can be seen as kingmakers.
You are creating some urgency where there is none. The lead time of around half a year for wafer orders is well known by now, and AMD is not waiting until the last second to make such orders.

I think AMD's modus operandi is pretty clear to see: They are involved with the leading edge nodes from the start, but the time isn't used for actual volume production, some GPU pipecleaners aside, but instead for adapting and optimizing the die for the node, to a point that AMD is reluctant mentioning TSMC's node names and rumors are now talking about optimizations being AMD specific and other TSMC customers wanting a part of it as well.

Now the questions are, how early did TSMC think 5nm was a homerun / working great. How early/did AMD/TMSC talk about accelerating to 5nm. What products does that line up to.
As pointed out before we should consider there to be a 1-2 years lead time minimum for a new/ported design on a new node. This means AMD was confronted with the decision of adopting 5nm early around 2 years ago. I don't think AMD back then would have been willing (even able?) to double its work on Zen 3 just to add a potentially redundant node. The logical choice back then would be accelerating what was already destined to be in the making for 5nm, and that's Zen 4.
 

maddie

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Because AMD so far wasn't a participant in any battle for leading edge wafers. They picked up/for consoles are still picking up 7nm when leading edge customers moved on to 5nm already.
Outside of Apple and a few others (Xilink?), AMD is pretty much an early user of premium wafers. Nvidia is now competing as they realize the threat of not booking early on a new node/process.

You are creating some urgency where there is none. The lead time of around half a year for wafer orders is well known by now, and AMD is not waiting until the last second to make such orders.

I think AMD's modus operandi is pretty clear to see: They are involved with the leading edge nodes from the start, but the time isn't used for actual volume production, some GPU pipecleaners aside, but instead for adapting and optimizing the die for the node, to a point that AMD is reluctant mentioning TSMC's node names and rumors are now talking about optimizations being AMD specific and other TSMC customers wanting a part of it as well.
Witness Nvidia's attempt to pretend that they are dominant backfire and their present scramble to book 7nm & 5nm wafers. Pretending that you can move at your own pace AND simultaneously have as many wafers as you need when you need them is delusional. Too many customers for too little product is the present reality. Sure, TSMC will add capacity but that takes time and makes you fall further behind your competitors. So yes, I do think there is an urgency not seen in recent times.

Witness RDNA having equivalent perf/W to Turing through node advantage vs pure architecture. Surely this is seen as a threat by Nvidia.

As I wrote earlier, if TSMC has capacity earlier than expected, what do they do? Sit on it until AMD decides to use it? Sell it to others and then tell them later, too bad, AMD now needs it?
 

DisEnchantment

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1590768113826.png

TSMC is cutting CapEx for wafer capacity increase due to potential lower orders from loss of business with Huawei. I suppose COVID-19 is effects are also coupled in there :confused:
Anyway, there are enough wafers around due to covid affecting demands for smartphones. So MTK, QCM, AAPL et al. are all slashing wafer bookings.


UPDATE:
News report denied by TSMC
 
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maddie

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View attachment 21798

TSMC is cutting CapEx for wafer capacity increase due to potential lower orders from loss of business with Huawei. I suppose COVID-19 is effects are also coupled in there :confused:
Anyway, there are enough wafers around due to covid affecting demands for smartphones. So MTK, QCM, AAPL et al. are all slashing wafer bookings.
Could one argue that AMD and possibly Nvidia might be two of the few (only?) large growth customers for TSMC presently?
 

DisEnchantment

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Could one argue that AMD and possibly Nvidia might be two of the few (only?) large growth customers for TSMC presently?
I think it would be fair to say AMD is going to be the single biggest customer for TSMC by end of 2020. AMD has 30K wpm booked from Q3, and in Q4 another 10-15K wpm additional on top of that.
And yesterday Lisa said wafer supply is still tight, so it seems AMD is still feeling uneasy with 45K wpm by Q4.
40-45K wpm is bigger than any of the other semi vendors, Apple included.

TSMC won't want to over commit and increase capacity for fear of under utilization.

Sources are Digitimes/Chia, they are reliable for most things TSMC/Taiwanese.
Most of those I have posted in this thread itself. I can edit it later if you wish.

EDIT:
AMD also happen to find itself on the better side of things when it comes to how the covid impacts are shaping up.
MS and Sony are going to keep their commitments
Cloud deployments are stable
Unexpected stability of the PC Market
Govt deals which already are providing development funds (ROCm for example got a decent cash injection from the US Govt. on top of Researcher and Scientist community contribution).
Samsung pays for RDNA development, at least some part of it as pertains to what they desire in the architecture (Development, Licensing and Royalty .. the clause says, similar to semi custom, I might have misread this one)

Added links to previous posts related to wafer allocations
I read the same thing, I asked @kokhua what is it for but there is no clarity.
30K wpm N7(+/P) from Q2 and then 12K wpm N5 from Q4.

I am wondering if the report is correct or it could be they mis quoted someone. For example it could be that AMD got extra wpm but does not mean N5 because the processes share a lot of common equipment and capacity taken out from N5 could be used for N7 for example.

However, if true ... :cool:
Sorry, Chia's translation is better, yours is mixing up some of the things.

- Huawei's 5nm cut is without a date. Capacity gap was filled by Apple anyway.
- For Q4 Apple asked TSMC to add 10k wpm 5nm (where it competes with AMD and others)
- TSMC has developed an enhanced 5nm specifically for AMD, which has a capacity requirement of no less than 20k 12-inch wpm (I think that just means having TSMC do some customization comes with the requirement of taking at least 20k 12-inch wpm, so that's what AMD takes)
- Huawei also lowered 7nm orders, which were filled by "big customers like Nvidia and AMD".
- As a result both 7nm and 5nm are fully booked until the end of the year.
- TSMC didn't comment on the report.

DeepL is pretty decent if you need to work with machine translations.
 
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beginner99

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And yesterday Lisa said wafer supply is still tight, so it seems AMD is still feeling uneasy with 45K wpm by Q4.
40-45K wpm is bigger than any of the other semi vendors, Apple included.
Which makes sense as the consoles SOCs are huge compared to iPhone SOC and volume will be big, not as big as iPhone obviously but I guess comparable in number of wafers as bigger die means lower yields as well.
 

DisEnchantment

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Which makes sense as the consoles SOCs are huge compared to iPhone SOC and volume will be big, not as big as iPhone obviously but I guess comparable in number of wafers as bigger die means lower yields as well.
Indeed. I made a comparison before and I list it here.
With a defect density of 0.1/mm2, each 300m 7nm wafer can give around
  • 125 XSX Console chips,
  • 104 EPYC/TR CPU (8-Chiplet)
  • 210 Navi 10
  • 80 Hypothetical Big Navi GPUs (505mm2)
  • 420 3900X (excluding IOD)
  • 840 3700X (excluding IOD)
or
  • 650 Apple A13 chips
 

UNCjigga

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So, it shakes out like this:

Zen3: impN7 CCDs for Epyc and low end Ryzen. N5P CCDs for High end Ryzen and maybe Threadripper. A pair of APUs, one with VEGA and one with RDNA.
Do you think the Zen3 APUs might be using N5P CPU chiplets in order to fit more cores/more CUs onto the substrate? I could see that being important for desktop APUs targeting mid-tier graphics performance. I'd expect the mobile APUs to continue to be monolithic N7P parts.
 

dr1337

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Do you think the Zen3 APUs might be using N5P CPU chiplets in order to fit more cores/more CUs onto the substrate? I could see that being important for desktop APUs targeting mid-tier graphics performance. I'd expect the mobile APUs to continue to be monolithic N7P parts.
I'm not the person you quoted, but my take is that a "chiplet APU" is inevitable. A zen 3/4 chiplet with a 24cu rdna2/3 chip on package next to it, maybe with a hbm2e shared l4/ram? Now that would be the perfect SoC for many, many customers.

With regards to the current rumors though I'm still not sure about zen 3 being on 5nm. If AMD really did recently acquire more fab capacity, then perhaps its a monolithic mobile APU like cezanne. An APU can take advantage of 5nm much more than a server or desktop chip, especially in mobile where power consumption really matters. Its is a weaker market for AMD and an accelerated response to tiger lake would make the most strategic sense IMO.
 

moinmoin

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Outside of Apple and a few others (Xilink?), AMD is pretty much an early user of premium wafers.
Qualcomm and HiSilicon (possibly MediaTek for Helio M70 as well) also used N7 earlier than AMD for its CPUs. AMD was an early (still not first mover though) user of N7 for MI50/MI60/Radeon VII. But at the time AMD CPUs on N7 went into volume production when the aforementioned companies already were preparing for newer nodes.

Nvidia is now competing as they realize the threat of not booking early on a new node/process.
That's distinctly Nvidia's problem who preferred to dual source theirs chips instead sticking with one foundry early on and getting to know the node from the start like AMD did.

Witness Nvidia's attempt to pretend that they are dominant backfire and their present scramble to book 7nm & 5nm wafers. Pretending that you can move at your own pace AND simultaneously have as many wafers as you need when you need them is delusional. Too many customers for too little product is the present reality. Sure, TSMC will add capacity but that takes time and makes you fall further behind your competitors. So yes, I do think there is an urgency not seen in recent times.
I'm honestly unsure why you even brought Nvidia into this discussion. Yes, Nvidia handled it badly. Incidentally they essentially did the opposite to what AMD did, so that's a good thing for AMD, isn't it?

Witness RDNA having equivalent perf/W to Turing through node advantage vs pure architecture. Surely this is seen as a threat by Nvidia.
That's so far off the rails now I don't know how to answer. Yes, Nvidia will want to react to that, duh?

As I wrote earlier, if TSMC has capacity earlier than expected, what do they do? Sit on it until AMD decides to use it? Sell it to others and then tell them later, too bad, AMD now needs it?
Does TSMC have a lack of capacity or does it have capacity? Please stick to one.

AMD naturally will order additional wafers on shorter notice if its has a use for them. You seem to have got the idea creating those chips is a just-in-time business, but we already know that the lead time for order fulfillment by TSMC can be over half a year.

AMD is already ordering and getting what it needs. The issue is not so much lack of capacity but the long lead time for order fulfillment which requires projection of demand for the products at that later time. AMD is rather conservative with those (as much as ~25% annual growth can be considered conservative) and said lead time prevents adaption to markets demand on shorter notice. Once slots at TSMC become available on shorter notice like now in case of the HiSilicon/Huawei drama you can bet that its customers including AMD will show interest in it depending on their needs.
 
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firewolfsm

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I'm not the person you quoted, but my take is that a "chiplet APU" is inevitable. A zen 3/4 chiplet with a 24cu rdna2/3 chip on package next to it, maybe with a hbm2e shared l4/ram? Now that would be the perfect SoC for many, many customers.
One of the reasons AMD went monolithic for the APU is power consumption for notebooks. The chiplet design has a power consumption disadvantage for I/O, it's not enough to really impact desktops but will definitely hurt battery life in thin and light laptops. Laptops are the most important market for the APUs, which is clear since AMD releases those first.
 

dr1337

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One of the reasons AMD went monolithic for the APU is power consumption for notebooks. The chiplet design has a power consumption disadvantage for I/O, it's not enough to really impact desktops but will definitely hurt battery life in thin and light laptops. Laptops are the most important market for the APUs, which is clear since AMD releases those first.
just fyi I am aware of this, I should have been more specific in saying that a "chiplet apu" would very much be a desktop class product. I could have also been clearer in that cezanne being on 5nm as a mobile product meant a monolithic design.

I do believe though that many OEMs would have interest in higher performance APUs, even with the higher power consumption.
 

maddie

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Qualcomm and HiSilicon (possibly MediaTek for Helio M70 as well) also used N7 earlier than AMD for its CPUs. AMD was an early (still not first mover though) user of N7 for MI50/MI60/Radeon VII. But at the time AMD CPUs on N7 went into volume production when the aforementioned companies already were preparing for newer nodes.


That's distinctly Nvidia's problem who preferred to dual source theirs chips instead sticking with one foundry early on and getting to know the node from the start like AMD did.


I'm honestly unsure why you even brought Nvidia into this discussion. Yes, Nvidia handled it badly. Incidentally they essentially did the opposite to what AMD did, so that's a good thing for AMD, isn't it?


That's so far off the rails now I don't know how to answer. Yes, Nvidia will want to react to that, duh?


Does TSMC have a lack of capacity or does it have capacity? Please stick to one.

AMD naturally will order additional wafers on shorter notice if its has a use for them. You seem to have got the idea creating those chips is a just-in-time business, but we already know that the lead time for order fulfillment by TSMC can be over half a year.

AMD is already ordering and getting what it needs. The issue is not so much lack of capacity but the long lead time for order fulfillment which requires projection of demand for the products at that later time. AMD is rather conservative with those (as much as ~25% annual growth can be considered conservative) and said lead time prevents adaption to markets demand on shorter notice. Once slots at TSMC become available on shorter notice like now in case of the HiSilicon/Huawei drama you can bet that its customers including AMD will show interest in it depending on their needs.
I suppose I'm the worst writer here for your misrepresenting almost everything I wrote.

Last first:

Why would TSMC expedite a node if the lead times are so long so as to make using it impossible? Might as well always hold back to the earlier projected 'use by' date as your customers won't be able to use it anyhow. I have no idea as when they would have known. 1 year ago that progress was being made faster than planned?

AMD (Lisa Su) recently stated (days ago) that wafer supply is still short. Make of that what you will, but it doesn't sound like being satisfied.

TSMC has been oversubscribed on 7nm and 5nm. The recent pandemic effect is totally unplanned unlike having months notice that a node is coming along quicker than expected. Please don't mix the two, they're separate effects.

The point with Nvidia not wanting to cede node leadership to AMD, as I'm sure you know is that he who is first to a node generally gets a huge advantage. In this case AMD's inferior architecture equals Nvidia in perf/W. This is merely an example and why I brought Nvidia into the statement. No other reason.
 

jpiniero

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Indeed. I made a comparison before and I list it here.
With a defect density of 0.1/mm2, each 300m 7nm wafer can give around
  • 125 XSX Console chips
I am pretty bearish on how well the consoles will do at launch given the economy and the expected high prices of the consoles. The PS4 sold 4.2 million consoles in 2013 and the XBox One sold about 3 million. I don't think either will come close to that. I suppose either wouldn't be too upset if they overbought since they could just cut orders later but depending on how long the lead time they give, even 10k wpm feels plenty for both. Maybe 15k if the lead time is shorter.

Edit: I guess my point is that while the consoles would require some amount of wafers, they would have to be gaining serious market share in some market to require 40-45k wpm.
 
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moinmoin

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Why would TSMC expedite a node if the lead times are so long so as to make using it impossible?
TSMC wouldn't expedite a node if there's no customer being ready to use it. And as I stated before I find it highly unlikely that AMD would port Zen 3 to it, time wise that's too close and business wise that would be unlike how AMD operated up to this point. And given AMD's resources back when the decision had to be made it's also unlikely, too close, and unlike how AMD operated up to this point that Zen 4 was expedited. It's a rumor, and it including AMD like that makes it unlikely to be real.

AMD (Lisa Su) recently stated (days ago) that wafer supply is still short. Make of that what you will, but it doesn't sound like being satisfied.
Yes of course she's not satisfied of not being able to fulfill the demand that is now there. AMD's projection of the demand doesn't match the actual demand now, of course AMD can't be satisfied about that and will adapt future projections accordingly. Su and AMD also said in the past that this is not a problem with TSMC, AMD has to get its order in line.

TSMC has been oversubscribed on 7nm and 5nm. The recent pandemic effect is totally unplanned unlike having months notice that a node is coming along quicker than expected. Please don't mix the two, they're separate effects.
I still think you haven't really realized in what space of time these events of expanding/reducing capacity and creating/adapting designs to nodes happen. We are not talking about weeks or months, but years for this to happen. TSMC being oversubscribed was not a matter of planing or malice on part of TSMC but due to the inadequacy of its competing foundries in Samsung Semiconductor and (indirectly) Intel. Your example of Nvidia is a good one here. It's also a recent event not yet reflected in realized investments.

The point with Nvidia not wanting to cede node leadership to AMD, as I'm sure you know is that he who is first to a node generally gets a huge advantage. In this case AMD's inferior architecture equals Nvidia in perf/W. This is merely an example and why I brought Nvidia into the statement. No other reason.
In the past Nvidia ceded node leadership to AMD several times actually. Polaris (14nm in June 2016) was essentially at the same time and node gen as Pascal (16nm in May 2016). Tahiti (28nm in January 2012) was earlier than 28nm Kepler (April 2012). Cypress (40nm in September 2009) was essentially at the same time as 40nm Tesla (October 2009). R600 (55nm in May 2007) was earlier than 55nm Tesla (July 2008). etc.

In the current round it was essentially a gamble with AMD betting on TSMC and Nvidia betting on Samsung Semiconductor, and the more reliable foundry brought the decision.
 
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HurleyBird

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I think it would be fair to say AMD is going to be the single biggest customer for TSMC by end of 2020. AMD has 30K wpm booked from Q3, and in Q4 another 10-15K wpm additional on top of that.
Does that include consoles? Because it's ambiguous how to count those in terms of pull with TSMC. They're sort of AMD even if they're technically Sony/MS.
 

LightningZ71

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@moinmoin, you are conflating AMD last year with AMD three+ years ago. When Zen hit the market, AMD was deep in the WSA with GloFo, who had been chronically behind other foundries. They were just barely working with TSMC at the time. They were definitely feeling the effects of being beholden to one foundry and one node at a time.

AMD publicly stated that they intended to never be in that situation again and we’re going to take steps to be flexible with both nodes and foundries. In addition to that, TSMC has also realized that supporting their customers during their various development phases will lead to better asset utilization, and have publicly discussed advanced development tool kits and their own engineering support for premier customers to enable them to go from design to volume production in shorter amounts of time.

This isn’t the same industry that it was just a few years ago. While design to production can still take years, parallel development isn’t as near impossible as it once was. TSMC announced N5P a year ago, and has been in risk production for a while if their hints from last year are to be believed. Assuming all of that is true, AMD had the needed information for N5P early last year. In a tight window, that’s enough time to hit HVP by 4q20.

I have no problem believing that AMD will have something being produced at full rate on N5P in the fourth quarter of this year. I personally think that it is going to be a zen 3 CCD. I don’t think that there will be a 5nm APU in HVP until 1H21.
 

DisEnchantment

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I am pretty bearish on how well the consoles will do at launch given the economy and the expected high prices of the consoles. The PS4 sold 4.2 million consoles in 2013 and the XBox One sold about 3 million. I don't think either will come close to that. I suppose either wouldn't be too upset if they overbought since they could just cut orders later but depending on how long the lead time they give, even 10k wpm feels plenty for both. Maybe 15k if the lead time is shorter.

Edit: I guess my point is that while the consoles would require some amount of wafers, they would have to be gaining serious market share in some market to require 40-45k wpm.
I agree. It seems like a fairly substantial jump.

But here's my theory
  • The IOD for Zen3 could possibly be fabbed by TSMC going forward. This could explain the jump in needed wafers because the IOD is not small.
    • Assuming worse density scaling than the CCDs because of the PHYs and IOs it will be bigger than the CCDs (80-100mm2 DT and 250-280mm2 EPYC)
    • This is bound to happen at some point. I am not sure GF can make the super dense micro bumps needed in the future for die stacking.
  • The cores and cache grew in size for Zen3
    • Zen --> Zen2 core saw a growth of ~36% in transistor count including L3 cache. Just the core with the L2 it grew 17%
    • An increase in the CCD die size of 15% lets say means AMD would need 15% more wafers even keeping demand at same pace. And yield would drop even more.
  • Additional wafer allocation for Q4 could be needed to cover additional products for Cezanne/Mobile APU. We know AMD has to be in time for OEM refresh otherwise they will miss the bus.
 
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Exist50

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Going to chime in with my 2¢. This N5P rumor seems like 100% BS, and I'm honestly confused why so many are taking it seriously. AMD needs to deliver on their roadmap as close as possible to be seen as a more reliable alternative to Intel, and thus pull away marketshare. They will have a substantial PnP and cost advantage even without 5nm, and they have a relatively small team and limited resources. Why on earth would they risk it all to be the first customer on a bleeding edge process? Best case scenario, they suffer a ~1 quarter delay to have an even more substantial lead over Intel. Worst case scenario, that stretches a few more quarters. At some point, they also run the risk of intersecting with Sapphire Rapids, which would eliminate any relative performance advantage 5nm would have given them.

No, Zen 3 will be on some variant of 7nm. Possibly 7+, but more likely 7P.
 

yuri69

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Going to chime in with my 2¢. This N5P rumor seems like 100% BS, and I'm honestly confused why so many are taking it seriously. AMD needs to deliver on their roadmap as close as possible to be seen as a more reliable alternative to Intel, and thus pull away marketshare. They will have a substantial PnP and cost advantage even without 5nm, and they have a relatively small team and limited resources. Why on earth would they risk it all to be the first customer on a bleeding edge process? Best case scenario, they suffer a ~1 quarter delay to have an even more substantial lead over Intel. Worst case scenario, that stretches a few more quarters. At some point, they also run the risk of intersecting with Sapphire Rapids, which would eliminate any relative performance advantage 5nm would have given them.

No, Zen 3 will be on some variant of 7nm. Possibly 7+, but more likely 7P.
Exactly this. AMD running full design cycles of a Zen SKU on both 7nm and 5nm is just wrong given their roadmap and cash balance.

They plan Zen 3 to be on a 7nm variant. For 5nm they have Zen 4 in 2022. This simply makes sense compared to these wild theories - use Occam's razor.
 

HurleyBird

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They plan Zen 3 to be on a 7nm variant. For 5nm they have Zen 4 in 2022. This simply makes sense compared to these wild theories - use Occam's razor.
Waiting that long to get their foot in the door for 5nm when they're competing for capacity doesn't sound like the best plan. They could have a GPU pipe-cleaner planned for 5nm prior to Zen 4, but the GPUs always seem to slip so I doubt AMD would rely on that.

If not initial Zen 3, then I would expect either a mid-gen Zen 3+ refresh, or some APU, to be on 5nm.

But honestly, my money (I'm at around 2/3rds probability in my head) is on parallel development of 7nm and 5nm for reasons I enumerated previously. And if this isn't what AMD is actually doing, it is what they should have done given hindsight of TSMC's present execution. Remember that we're likely talking about dies in the ballpark of ~55mm2 with somewhere around 2/3rds (or even more) of that being cache. You could go as far as to say that not aggressively pursuing leading nodes would be ignoring one of the greatest advantages of chiplets.
 
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An aspect that I think could speed up the timeline is that perhaps AMD had Zen 3+ already planned and started developing with it potentially targeting TSMC 5nm. So its less that they're migrating Zen 3 to 5nm but rather are accelerating Zen 3+ because of opportunity to get 5nm earlier. They likely already have some substantial development started, and TSMC might help them to accelerate things even quicker. And they already have some Zen 3 produced on 7nm, so in some ways it'd be like a die shrink which should simplify things a bit, further compressing the development timeline.

I think it might even be potentially beneficial for AMD that production be kinda drawn out. Meaning, They get enough chips to launch the highest end Ryzen at the start of the year. Then a month or two later they launch the next rung down. And then the next. That takes say 6-8 months. By then, the process will have matured and improved, so they could then, either through just binning over that time span and because of the chiplet approach so they were producing the same chiplet just the cheaper ones had to build up enough defective chiplets and/or the production cost drops, that they also happen to have higher quality chiplets that they could then sell as a refresh. And then, depending on various factors they could either be primed for Zen 4 production or let the refreshed stuff carry them through the year.

With regards to them going with Vega yet again on the next APU, I think there's likely benefits for APUs to having consistent hardware. And you're generally limited quite a bit by other things such that you're not losing that much compared to the newest architecture for integrated GPU. So, we see them roll with Vega for what 3 generations, then they switch to RDNA2. I've posited before that the APU markets might value compute capability of Vega enough such that it was the tipping point, and since it already offered or they could tweak it to offer "good enough" performance for the graphics part of an APU, while it gives the CPU side consistent hardware to utilize/improve to maximize the total APU performance. And perhaps RDNA2 is where the compute capability doesn't take a step back.

Speaking about not being constrained by fab partners, I was just thinking about how the Samsung partnership could be interesting in another way. So, AMD develops GPU IP and then Samsung builds off of it, but likely tune the chips for efficiency and optimize for mobile market (meaning GPU but not overbuilt since it'd be constrained by thermal and battery). But what if AMD takes the Samsung SoC and slap it on an APU with a Zen based CPU chiplet, where the GPU would be enough. It could open up different product stack and features with little risk to AMD, where if they don't find a market for those features then they're out nothing, they would still be able to use it just for the GPU. But even for GPU performance it could be meaningful, like stacked DRAM for instance, where the GPU portion is then getting the full bandwidth of the stacked memory, alleviating memory bandwidth issues within the APU. Of course it could offer hybrid systems where when mobile it could go into an ARM mode for maximizing battery life, and then plugged in or in other mode it'd run Zen. It would also bring in the AI processing hardware that AMD's stuff has been lacking (and Samsung would be developing that so it wouldn't take resources from AMD while making Samsung's hardware more ubiquitous). And it'd bring cellular capability (although I might be mistaken and Samsung hasn't integrated their cellular modem into their SoC?). It also could give AMD the ability to offer mobile console options (Switch comes to mind, but they could offer a similar product to Sony and Microsoft for an option where it'd likely be especially good for the transition to game streaming, and that could potentially be the avenue for the hybrid processing that Microsoft considering, only it'd be where you have your console at home do a lot of processing but say you could support more than 1 portable console locally).

My previous theory has always been N7P, but now with everything leaking around like no tomorrow I am not sure.
My thinking was that
  • The whole narrative about IOD not scaling at all while not untrue does not paint the complete picture. Renoir is proof of this. And TSMC's numbers also indicate the density gains for PHYs, analog blocks etc to be around 20-30% which are far less than the 80% gain in SRAM density but tangible nonetheless(vs previous node). They could make the IOD on N7
  • Using everything TSMC, including IOD, is probably better, in that logistics are going to be slightly better, everything is fabbed at TSMC.
  • A smaller IOD would leave lots of wiggle room for core and cache design. This means HP cell libraries could be feasible, for desktop at least, since the CCDs can be a bit bigger.
  • If Renoir is anything to go by, a density gain of 20% over Zen2 CCD is guaranteed. There was no real frequency regression.
  • Will server CCDs be same as desktop CCDs. Or will there be two sets of HP(Lower density performance oriented) and HD (Higher density efficiency oriented) CCDs, or will the Zen3 CCDs be same at all.
If Zen2 HD libs can hit 4.4 GHz, the HP cells would definitely hit 4.8+ (TSMC's own estimates). Add to that increased die area available from a potential usage of TSMC IOD. There would be room for larger caches and wider cores.

Will the WSA get in the way of innovation. Will the Zen3 designs use anything from GF at all? Lisa mentioned yesterday that Rome will be very much in production next year as well, add to that, the Pro and embedded series, there is a good chance they could meet these WSA obligations without constraining Zen3 chiplet designs by sticking with GF.

Of course Mobile is a different game, and it would make sense to move to N5(P)
I don't think AMD is concerned about the WSA much at all, as they have plenty of leverage. Plus couldn't they produce say chipset and other products at GF? I think there might be other potential there as well (interposers or similar?). Could also work deals for partners (like say someone has an FPGA or something). And I think there could be a wealth of potential embedded options. Zen based tinker boards. Maybe combine some Zen cores with an FPGA. With GF's 12nm that's good for wireless stuff, its possible that AMD could license some wireless IP and produce some of their own stuff, so that they could sell full stack solutions like Intel does. I might be mistaken but I think 12nm is the process that HBM3 is targeted for.

And some of it they could start at GF, and then move production somewhere else (Samsung, for instance, where Samsung could probably give them an idea of the benefit they'd see from going from the GF - which was based on Samsung's - 14/12nm to newer processes).

I'm not saying any of that stuff is likely, but there's definitely options for them to utilize GF.
 
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