inclusive means L1/L2 data is copied to L3.
L2 doubling to 1MB seems like a very good bet. And semi-decent chance L1 growing too.
Seems they took the all roads lead to Rome theme further in Zen3 by doing this at the scale of the CCX.
Does Zen2 follow Zen1 in L3 being victim cache?
For Zen3 the L3 cache unit may be a complex compound of its own and also now may have the role of acting as hub. It may be a smart hybrid thing that is not one or the other; internally it may dedicate a good fraction ~30% capacity as L4-ish victim cache (with L3 = hub+L3+L4).
inclusive would help in its role as hub when there are shared memory addresses being updated by several cores (more energy efficient, less latency than exclusive, but you have slightly smaller total cache footprint: 32 MB vs a 36 or 40 MB. something more flexible (non-exclusive or
partially-inclusive) based on whether addresses are shared between cores would have best of both worlds.