Speculation: Ryzen 4000 series/Zen 3

[Ajay]

Sandbagging AMD is best AMD.

Forrest made quite the claim there. We'll see, I'm excited for what this ends up being like for AM4 next year.

Well, Ryzen 4700X is going to knock the i9 9900k off the top step in ST and widen the lead in MT. It’s going to be a proper bashing. And, as an aside, I hope the new chipset for next year runs cooler so that the fans can be dropped. Kinda wish my PC wasn’t dying - I’d squeeze a bit more life out of it for a chance at Zen3.

 

[itsmydamnation]

Just haters are so blind they cannot read between the lines....
Funny how all haters are surprised or silent now

Who are the haters and who is silent? You realise that a new uarch would be far more complex then just adding some alus you have such a hard on for right?

You still haven't produced one piece of evidence supporting your claims of 4xalu being a bottleneck. Why did they add a3rd agu in zen2 instead of added a 5th alu if alu is such a bottleneck?

Edit:also agu was much harder to add, they had to unify the Scheduler and it connects to the memory sub system, much harder then read/write to the prf.

 

[soresu]

It’s going to be a proper basing.

Did you mean basting?

 

[DisEnchantment]

1. AMD Zen2 optimization document revealing Zen2 is last 17h Family... suggesting Zen3 will be new Family number, new uarch
2. Zen3 is coming way early after Zen2 .... suggesting parallel development rather than successor
3. process node 7nm EUV which is way too complicated when compatible and easier and cheaper nodes like N7P or N6 are available (only completely new uarch makes sense from economy point of view, especially with easy direct path to 5nm EUV).
4. Lisa Su mentioned AMD is focusing on architecture development more than on process node.

I would agree on these points to some extent, the others I don't want to comment, too uncertain at this point.

 

[Ajay]

Did you mean basting?

Bashing. Must have typed that on my iPad.

 

[maddie]

Unless my reading glasses have suddenly malfunctioned, IPC changes will not be as large as Zen2 produced. Also, I didn’t see where anything was said about large clock increases. The 7nm+ process just doesn’t offer that much frequency headroom.

You understanding of his statement is incorrect.

In effect he stated that the increase normally expected from an evolutionary improvement was exceeded in Zen2 due to additional architectural improvements, BUT Zen2 to Zen3 will bring a normal step change seen by a new layout or design, which is NOT a marginal increase.

Expect similar but probably larger than 15% this round.


Is it confirmed that AM4 remains relevant for Zen3?

 

[moinmoin]

Is it confirmed that AM4 remains relevant for Zen3?

Milan (Zen 3 based Epyc 3) will still be on the same socket so common assumption so far is AM4 doesn't change either. (Then again the socket compatibility change for Threadripper 3 was unexpected as well.)

 

[Ajay]

You understanding of his statement is incorrect.

In effect he stated that the increase normally expected from an evolutionary improvement was exceeded in Zen2 due to additional architectural improvements, BUT Zen2 to Zen3 will bring a normal step change seen by a new layout or design, which is NOT a marginal increase.

Expect similar but probably larger than 15% this round.


Is it confirmed that AM4 remains relevant for Zen3?

You are tilting against the wind my friend. You may want to read my follow up post.

 

[soresu]

Bashing. Must have typed that on my iPad.

Hahahah, figures that my mind would go to the wrong alternative - working in a kitchen with chefs for years will take your mind to dirty places.....

 

[soresu]

Then again the socket compatibility change for Threadripper 3 was unexpected as well

The only promise I can remember being given related to AM4's 2020 CPU compatibility.

 

[soresu]

Zen3 is coming way early after Zen2 .... suggesting parallel development rather than successor

The existence of leap frogging CPU design teams has already been stated officially by AMD.

Also just because Zen2 was evolutionary doesn't necessarily mean it could not be part of a leapfrog effort.

It seems unlikely that the same people are involved in the deep layout and uArch design as are used for the final bring up phase to polish off each uArch variant for tape out and production.

ie once the major design phase is finished, the core is handed off to a finishing team, while the design team carries on to the next core on the drawing board.

 

[soresu]

first Zen3 leak on May from YT Moors Law Dead, suggesting Zen3 is SMT4, and Zen2 Treadripper about end 2019/early 2020 and maybe canceled in favor of Zen3 while AMD concentrating Zen2 chiplets for server EPYC.... a lot of haters verbally attacked this guy however his sources was right, TR2 will have 2020 availability rather than promised Oct. Honestly I wouldn't be surprised Zen3 will have SMT4 feature as his source was right.

TR2 is Zen+ Threadripper, or Ryzen Threadripper 29xx.

TR3 is Zen2 Threadripper, or Ryzen Threadripper 3960X -> 3990X.

I wouldn't get your hopes up about SMT4, I'm really leaning towards leaker bait as an explanation for that.

 

[Richie Rich]

Who are the haters and who is silent? You realise that a new uarch would be far more complex then just adding some alus you have such a hard on for right?

You still haven't produced one piece of evidence supporting your claims of 4xalu being a bottleneck. Why did they add a3rd agu in zen2 instead of added a 5th alu if alu is such a bottleneck?

Edit:also agu was much harder to add, they had to unify the Scheduler and it connects to the memory sub system, much harder then read/write to the prf.

Adding some ALUs is not trivial task. Actualy this is the most difficult task in CPU development. You need new pipes with schedulers, new algorithms how to distribute instructions and extract more paralelism in the same time, rebuilt front-end too. You are completely wrong. I gave you the SPECint2006 numbers showing Apple Vortex and Monsoon cores with 6xALUs are performing far better that anything with 4xALUs from Intel, AMD or its own Apple A10. BTW the 3rd AGU of Zen2 is not equal to other two AGUs, its for store only. However according to IPC performance numbers the Apple ALU:LSU ratio of 6:2 looks like more powerfull than AMDs 4:3 ratio. So I would suggest that AMD will go to 6:3 ratio with Zen3 as the most probable and pretty well balanced configuration.

I would agree on these points to some extent, the others I don't want to comment, too uncertain at this point.

Uncertain for people with lower knowledge. More you know easier to see where to go. There is nothing bad about speculation and brainstorming.

 

[DrMrLordX]

Zen3 is coming way early after Zen2 ....

Howso? Rome has been shipping to select cloud partners in non-trivial amounts since Q1 or early Q2 2019. Those guys got to see early Rome before any of us retail losers got our hands on Matisse. Milan will probably follow the same path, and we'll see Vermeer in maybe July 2020 if all goes well.

process node 7nm EUV which is way too complicated when compatible and easier and cheaper nodes like N7P or N6 are available (only completely new uarch makes sense from economy point of view, especially with easy direct path to 5nm EUV).

That's ridiculous. TSMC 7nm+ offers a 20% increase in density and 10% increase in performance at isopower. Zen3 is AMD's bread-and-butter for 2020. Why would you not put your next design on the best node available from your fab partner? It's not like 7nm+ is a "boutique" node (like the node GF inherited from IBM for POWER8). Mobile chips are launching on this node. It's very mainstream, and for what you get, it's reasonably priced.

Apple A12/A13 Vortex CPU core with 6xALUs showed that there is huge potential for IPC gain going wider core

Broken record.

first Zen3 leak on May from YT Moors Law Dead, suggesting Zen3 is SMT

Broken record.

and Zen2 Treadripper about end 2019/early 2020 and maybe canceled in favor of Zen3

TR3 just launched, availability on the 25th. So that is just flat-out not true.

a lot of haters verbally attacked this guy however his sources was right

Obviously not.

TR2 will have 2020 availability

TR2 launched last year. TR3 is already launched with availability in six days.

edit: oh, by the way, in case you hadn't noticed:

Info - Threadripper 3rd gen was already used for the Terminator Movie

Looks like some had very early access to this new TeRminator 3 platform Did they wait for release because of motherboard delays?

forums.anandtech.com

Considering that movie just came out a few weeks ago, the studio that developed the film using TR3 had to have had TR3 months ago.

 

[Richie Rich]

@DrMrLordX: Are you psychopath? You try piece by piece to prove that my prediction of Zen3 being new architecture was wrong.... day after AMD's server leader Norrod confirmed that Zen3 is actualy complete new architecture. It's not my fault you cannot read between the lines.

The same is Soresu. TR2 is TR based on Zen2. I like numbering in proper order, single digit is uarch generation. Jesus Christ, I'm not wonder why you guys cannot put all the puzzles toghether. You are blind by hate.

And last thing. YT channel Moors laws not dead was right about Zen2 TR timing so we can expect SMT4 for Zen3 too. I would say the probability raised from 60% to 80% now.

Calling out users and insulting them
is not allowed in the tech forums.

AT Mod Usandthem

 

[amrnuke]

@DrMrLordX: Are you psychopath?

I'd try to refrain from name-calling. It makes you look like the less intelligent one.

You try piece by piece to prove that my prediction of Zen3 being new architecture was wrong.... day after AMD's server leader Norrod confirmed that Zen3 is actualy complete new architecture. It's not my fault you cannot read between the lines.

You do know the difference between node and uarch, don't you?

The same is Soresu. TR2 is TR based on Zen2. I like numbering in proper order, single digit is uarch generation. Jesus Christ, I'm not wonder why you guys cannot put all the puzzles toghether. You are blind by hate.

So you call the 2990WX TR1? What do you call the 1950X? TR0? Maybe YOU can't put the puzzle pieces together because you can't keep things straight in your own head.

And last thing. YT channel Moors laws not dead was right about Zen2 TR timing so we can expect SMT4 for Zen3 too. I would say the probability raised from 60% to 80% now.

No, the YT clickbaiter was not right about TR3 timing. He said early 2020. It's already been available to many for months now. And it's launching to the public at-large on Nov 25, not early 2020. The YT channel was false. The only thing they were right about was the TR3 would be delayed, which wasn't hard to figure out, and said channel wasn't the first or only one talking about a TR3 delay. And to then make the statement that because that YT channel was right (they weren't) then we must expect SMT4 for Zen3 (which makes no sense) is just silly. If you're so sure, make it 100%, and if you are wrong, you will self-ban from posting any speculation about Zen4.

 

[Topweasel]

I'm not currently capable of reading the quotes as written as supporting your point of view.


Zen1->Zen2 IPC increase was larger than typical of an evolutionary upgrade. Zen2->Zen3 is typical of an entirely new architecture. The only way I see to support your line of thinking here is to claim that the Zen2 IPC increase was not just larger than the typical evolutionary upgrade, but also larger than an upgrade in architecture. That is not what was said. It may be true, mind you, but that isn't what is claimed in the article.

Well keep in mind that this happens from time to time. Take Nahalem vs Conroe. Architecturally the only real changes were the move to an IMC and removal of the front side bus. Comparable to AMD working more on the interconnect on their chips rather then making wholesale changes to their core which came later in Sandybridge.

Nahalem was about at worst 15% faster per clock. Most of the time 20-30% faster. Sandy Bridge in replacing Nahalem had a couple of things it really jumped out on was closer to a 10% upgrade. Maybe 15% if you want to stretch it. The former an improvement on a previous uarch fixing connectivity issues, and the other not necessarily from the ground up but a major uarch change.

Zen3 could be AMD's Sandybridge. A well defined change in uarch. But still not as drastic a development as cleaning up the connectivity with Zen2.

 

[dnavas]

...you will self-ban from posting any speculation about Zen4.

It is a speculation thread, doesn't this seem overly harsh?
I don't know enough to know the art of possible, but it isn't outside my capabilities to judge deliveries. Although nVidia was fond of referring to cores as either "low latency" or "high throughput", it's been interesting to watch AMD add throughput to their low latency cores, at a relative (to competition) cost of latency (for low core-count use-cases). Zen3 is not a higher core-count product, so either they're working on increasing their throughput in other ways (in which case something like what Rich has described isn't complete insanity), or they're going to tackle latency (in which case it's a distraction). From what I've gleaned, SMT4 was something looked at, but not adopted :shrug:

It also remains to be seen how revolutionary this design really is. I mean, if they've designed a locally clustered, distributed, asynchronous/clockless ALU, well, that would be revolutionary, but I don't think they're aiming quite so far.

Despite my earlier response to Ajay, I hadn't expected this round to have appreciable IPC increase. It has been my long-held opinion that this round was actually an efficiency round meant to recapture the laptop market. I don't see evidence of that, though (at least for the laptop piece). If that were the case, I would have expected Milan to be pushed out some with an earlier drop date for down-market/integrated Zen3 products. I don't see that in the schedule, so :shrug: wrongo.

The problem I have retreating back to yet-another-throughput oriented round is that the 3950, like the 2990, strikes me as increasingly memory bandwidth limited. Making that situation worse seems unwise. In which case I'm forced to wonder what it is that they are working on. I assume they'll work on idle power consumption, laptop-oriented or not. But latency is the thing that makes the most sense to me. The kind that I would optimize is more alu<-->mem, but I wouldn't expect an IPC bump out of that :shrug:

We do know that one of the things Zen3 brings is some form of at-rest memory crypto for higher security (sorry, details have fallen out of my head). Are there other improvements we could expect from an increased attention to the mem i/o side of things?

 

[.vodka]

Is it confirmed that AM4 remains relevant for Zen3?

Milan uses DDR4, Genoa (Zen4) uses DDR5.

I don't think they're going to radically change Zen2's system architecture, so AM4 Zen3 should just upgrade the CPU chiplets and improve the current DDR4 I/O die (lower power, etc) while they're at it.

 

[krumme]

From my user perspective I dont really care.
If they revamp the entire memory subsystem and tune bits and pieces it will be stronger in gaming while not beefing the core radically up. Lean and mean but also not expensive. Suits mobiles and my gaming focus fine.

If they widen the core in a more radically new core that will be fun to watch, but it will come at a cost. Dont know if it will be worth it. We dont get the fmax speed increase and double cores as with zen 2.
Heck anyways judging by the remarks we are in for a treat regarding ipc.

As Lisa said, Amd focusing on design, and yet have mature 7nm euv and 5nm just in front of them - tock tock. Man...next 2 years is going to be fun.

 

[maddie]

It is a speculation thread, doesn't this seem overly harsh?
I don't know enough to know the art of possible, but it isn't outside my capabilities to judge deliveries. Although nVidia was fond of referring to cores as either "low latency" or "high throughput", it's been interesting to watch AMD add throughput to their low latency cores, at a relative (to competition) cost of latency (for low core-count use-cases). Zen3 is not a higher core-count product, so either they're working on increasing their throughput in other ways (in which case something like what Rich has described isn't complete insanity), or they're going to tackle latency (in which case it's a distraction). From what I've gleaned, SMT4 was something looked at, but not adopted :shrug:

It also remains to be seen how revolutionary this design really is. I mean, if they've designed a locally clustered, distributed, asynchronous/clockless ALU, well, that would be revolutionary, but I don't think they're aiming quite so far.

Despite my earlier response to Ajay, I hadn't expected this round to have appreciable IPC increase. It has been my long-held opinion that this round was actually an efficiency round meant to recapture the laptop market. I don't see evidence of that, though (at least for the laptop piece). If that were the case, I would have expected Milan to be pushed out some with an earlier drop date for down-market/integrated Zen3 products. I don't see that in the schedule, so :shrug: wrongo.

The problem I have retreating back to yet-another-throughput oriented round is that the 3950, like the 2990, strikes me as increasingly memory bandwidth limited. Making that situation worse seems unwise. In which case I'm forced to wonder what it is that they are working on. I assume they'll work on idle power consumption, laptop-oriented or not. But latency is the thing that makes the most sense to me. The kind that I would optimize is more alu<-->mem, but I wouldn't expect an IPC bump out of that :shrug:

We do know that one of the things Zen3 brings is some form of at-rest memory crypto for higher security (sorry, details have fallen out of my head). Are there other improvements we could expect from an increased attention to the mem i/o side of things?

I really don't understand this sometimes repeated reasoning.

Cores constant, efficiency much improved, but performance slightly improved. Unless AMD is willing to waste the infrastructure investments of present customers in Zen2 by dropping the TDP of Zen3, then we must assume that performance and efficiency are directly related, once TDP is constant.

edit :corrected mistake

 

[Hitman928]

Hello! Please tell me who is now in the lead Ryzen or i9?

Depends on what you want to do with them.

 

[uzzi38]

It has been my long-held opinion that this round was actually an efficiency round meant to recapture the laptop market. I don't see evidence of that, though (at least for the laptop piece)...

...I assume they'll work on idle power consumption, laptop-oriented or not.

Renoir will do that absolutely fine. Look at the SL3 and compare idle power there to SL2. Then realise the vast majority of idle power deficit between the two will come out of LPDDR4x support.

Plus, 7nm's efficiency will mean Renoir will slap around Tiger Lake in multi-core perf and efficiency in heavy workloads. The latter will probably lead in ST, but who cares, Renoir is aimed to take on Comet Lake as 10nm is ever irrelevant.

The problem I have retreating back to yet-another-throughput oriented round is that the 3950, like the 2990, strikes me as increasingly memory bandwidth limited.

In specific workloads yes. See Anandtech's review on the 3950X, for most people the bandwidth is fine. If you need more, then fear not, as AMD will without a doubt work on IF further. They have to if they want to get it to EMIB level of power efficiency. With Zen 2 they hugely improved bandwidth and reduced power per bit by 27%, there'll be more with Zen 3.

 

[Topweasel]

Laptop is the smallest worry for AMD at this point. Intel has allowed them to push TDP in server space by quite a bunch. Efficiency matters because Density matters to AMD. But removing themselves from any kind of 4S space, means density isn't even a worry unless they shooting for 2s 128c 1U systems at no to little performance loss. Clocks stay about even, maybe increase slightly or decrease slightly dependent on how the process develops or tweaks to uarch for increased clocks.

Then we look at Zen vs. Zen+. We didn't get a new Epyc even though we got a new TR. If anything the improvements to Zen+ should have worked more wonders on the efficiency table and allowed for dramatic increase in clocks on full spec'ed 32c EPYCs. Here we have no additional cores, maybe better efficiency, stagnate clocks, yet there is a Milan on the roadmap.

There is a balance here. But performance must increase. Otherwise if they they didn't make a Zen+ Epyc even thought they used the same tooling they would use for EPYC on TR2. Then they wouldn't be pushing out a new EPYC chip. All these can't be right. Either Zen 3 has higher IPC (enough to impact sales enough to do the validation), more cores, or increased clocks (with enough impact in sales to make it worth validation).

 

[uzzi38]

There is a balance here. But performance must increase. Otherwise if they they didn't make a Zen+ Epyc even thought they used the same tooling they would use for EPYC on TR2. Then they wouldn't be pushing out a new EPYC chip. All these can't be right. Either Zen 3 has higher IPC (enough to impact sales enough to do the validation), more cores, or increased clocks (with enough impact in sales to make it worth validation).

Erm, just a quick point, but a Zen+ EPYC would only be different in process node. The 'IPC' gain of 3% that Zen+ Ryzen had was because of a change that made it to both Threadripper and EPYC, but not Ryzen afaik.

Main reason there wasn't a Zen+ EPYC was because there basically was nothing else to offer.