IPC varies by a large amount across applications. Some applications may get a big boost from the completely reworked cache hierarchy while others may not. A 20% boost is a bit over optimistic, I think. There could be some applications that get a big boost from certain architectural improvements though. They could expand the AVX again which would also require increasing bandwidth again. I don’t know if they will support AVX512. I have always considered widening the width to 512 to be a bit of a kludge. Things that can take advantage of such wide vectors would be better off on a gpu. Intel didn’t have a gpu at the time, so AVX512 was their way of trying to get a cpu to behave like a gpu.My expectation for Zen3:
- IPC uplift ~20% (based on Norrod's comments this will be a true generational leap as core is based on a new uarchitecture' there will be radical changes in the pipeline structure, reduced latencies for instructions, increased ALU/FPU/AGU counts, other structures increased to accommodate the changes)
- clocks 5-7% higher
- core count 25% higher (10 chiplets x 8 cores; CCX is 8 cores sharing huge L3 cache)
- power draw roughly the same or slightly higher than Rome
- *possibility* of SMT4, not excluding it yet
This will put a stop to any gain Tigerlake/Icelake will make over SKL/X core. I think that the only advantage intel will have is going to be AVX512 and that's it. Everything else will be roflstomped by Milan.
They are focusing on efficiency, which actually allows for higher clocks in power constrained packages. With a new design on a new process variant, even AMD may not know what clocks they will be able to hit. I don’t really expect more cores with this generation. I think they are just going to have very large cache chips for HPC. The die would get a bit larger with 48 or 64 MB L3 and that will take up the available space on the Epyc package. The 32 MB die may not be any larger though. The current Zen 2 die is 2 core clusters with 4 cores each and 16 MB per core cluster. That is 8 cores total and 32 MB L3 total. Zen 3 will be 8 cores with 32 MB per die, so it is actually the same, just arranged differently. They will get a shrink with 7nm+, so it may be a similar size, even with new features. If the latency has gone up for L3, they may want larger L2 though. Cache shrinks well though, so I am still expecting relatively small die.