Speculation: Ryzen 4000 series/Zen 3

[Caveman]

Sorry, but I'm a noob at this threads technical jargon... Just looking to cut to the chase for my next build.

Every few years I build as powerful as a system as possible to support flight simulation. Current build is an Intel 4770k with a 1080Ti. I know single core performance is the key to flight simulation code (at least right now) but some of my favorite sims (DCS, and XP11) are migrating over to Vulcan.

1) Does Vulcan help justify an AMD chip more?
2) By Ryzen 3, do you think the AMDs single core performance will be equivalent to 9900k?
3) What is the estimated date of the first Ryzen 3s (4000 series)?

The first rig I built was an Athon because it was the fastest for flight simulation at that time. I really want my next build to be Ryzen.

 

[DrMrLordX]

1) Does Vulcan help justify an AMD chip more?

Maybe, maybe not. You're really going to need to wait for benchmarks.

2) By Ryzen 3, do you think the AMDs single core performance will be equivalent to 9900k?

You mean Zen3/Ryzen 4000? Zen2/Ryzen 3000 is already pretty close. Zen3 may put AMD over the top. We'll see. You're talking about specific niche applications, so it's going to come down to a title-by-title basis.

3) What is the estimated date of the first Ryzen 3s (4000 series)?

Since Zen2 was delayed until July 2019, Zen3 is probably going to be July 2020, pending further delays.

 

[Caveman]

DrMrLordX,

Thanks. Product Numbering systems these days seem somewhat complex/convoluted but my understanding is that Ryzen 2 (3000 series) is what is currently being sold and that Ryzen 3 (4000 series) is what's "coming next" (the one that this thread is about) and will already be released by this time next year. Does that sound right? I'm interpreting what you wrote as that...

 

[Atari2600]

Sorry, but I'm a noob at this threads technical jargon... Just looking to cut to the chase for my next build.

Every few years I build as powerful as a system as possible to support flight simulation. Current build is a 4700k with a 1080Ti. I know single core performance is the key to flight simulation code (at least right now) but some of my favorite sims (DCS, and XP11) are migrating over to Vulcan.

1) Does Vulcan help justify an AMD chip more?
2) By Ryzen 3, do you think the AMDs single core performance will be equivalent to 9900k?
3) What is the estimated date of the first Ryzen 3s (4000 series)?

The first rig I built was an Athon because it was the fastest for flight simulation at that time. I really want my next build to be Ryzen.

Your gonna need to wait for benches, but one thing to consider when you do have the benchmark information is - you buy a good X470 or X570 motherboard, and you'll be able to drop in a Zen3 mid-life upgrade in a couple of years time.

So, if (say) the 3800X was <5% FPS down on a 9900k, its probably a fair bet that any future 4800X (to pick a random name) may reverse that.
Conversely, if the 3800X is >5% FPS down on a 9900k, its unlikely Zen3 will reverse that either at all or enough to justify the performance hit prior to the upgrade.

Hopefully the benchmarks that you will have at some point will also include the 1800X or 2700X - so you can get an idea of what kind of step a Zen3 might be for your software.

edit, just seeing your subsequent post.

1800X => Zen 1.0, 8C top-of-range CPU
2700X => Zen 1.1, 8C top-of-range CPU
3800X => Zen 2.0, 8C CPU (not absolute top of range, but top of 8C parts)
4?00X => Zen 3.0, 8C CPU (definitely not absolute top of range - yet to be released product)


[There is no Zen2.1 on the horizon.]

 

[Caveman]

Atari2600,

Thanks for info. I actually want to build a system as early as Dec.

I've edited my OP to clarify I currently have a 4770k. I follow your logic exactly and is what I was assuming to be the case. If benches show I'm only giving up 5% (or even 10%) behind a 9900k now and the AMD boards are upgrade-able, then I have no issue upgrading to see maybe a 10% CPU bump from 4770k to 3800X or something... Then a bigger bump in another year or 2 when the next gen Ryzens hit bringing me ~10% OVER what the 9900k does now in single core apps. And, get the bonus of the multicore power (though I basically just use my flight sim rig for that and as a HTPC)...

Does all this sound in the right ballpark of planning?

 

[scannall]

Atari2600,

Thanks for info. I actually want to build a system as early as Dec.

I've edited my OP to clarify I currently have a 4770k. I follow your logic exactly and is what I was assuming to be the case. If benches show I'm only giving up 5% (or even 10%) behind a 9900k now and the AMD boards are upgrade-able, then I have no issue upgrading to see maybe a 10% CPU bump from 4770k to 3800X or something... Then a bigger bump in another year or 2 when the next gen Ryzens hit bringing me ~10% OVER what the 9900k does now in single core apps. And, get the bonus of the multicore power (though I basically just use my flight sim rig for that and as a HTPC)...

Does all this sound in the right ballpark of planning?

Seems to make sense. I would also note that the new Flight Sim from Microsoft is now in beta, and should be a lot more multi-core friendly. The beta sign-up is here.

 

[Topweasel]

Atari2600,

Thanks for info. I actually want to build a system as early as Dec.

I've edited my OP to clarify I currently have a 4770k. I follow your logic exactly and is what I was assuming to be the case. If benches show I'm only giving up 5% (or even 10%) behind a 9900k now and the AMD boards are upgrade-able, then I have no issue upgrading to see maybe a 10% CPU bump from 4770k to 3800X or something... Then a bigger bump in another year or 2 when the next gen Ryzens hit bringing me ~10% OVER what the 9900k does now in single core apps. And, get the bonus of the multicore power (though I basically just use my flight sim rig for that and as a HTPC)...

Does all this sound in the right ballpark of planning?

Pretty much the they can slide around a bit. But yeah 3-5% behind on most tools, 10% that are overly optimized for Intel. You probably will see more of a jump from the 4770 to 3800 though unless you are overclocking. Ryzen 3k is probably 8-10% better IPC and clocks a little higher. Thinking you will push a 15% bonus besides the obvious doubling up on cores. I went from a 4770k to a 3900x, its a dream.

 

[amrnuke]

Atari2600,

Thanks for info. I actually want to build a system as early as Dec.

I've edited my OP to clarify I currently have a 4770k. I follow your logic exactly and is what I was assuming to be the case. If benches show I'm only giving up 5% (or even 10%) behind a 9900k now and the AMD boards are upgrade-able, then I have no issue upgrading to see maybe a 10% CPU bump from 4770k to 3800X or something... Then a bigger bump in another year or 2 when the next gen Ryzens hit bringing me ~10% OVER what the 9900k does now in single core apps. And, get the bonus of the multicore power (though I basically just use my flight sim rig for that and as a HTPC)...

Does all this sound in the right ballpark of planning?

FS2020 in development will leverage more cores. If you're building before 2020, and you're looking completely top-end, then I'd suggest waiting for benchmarks on the 3950X. If you're only looking to be within 5% of the top tier in performance, then a 3600 or 3700X might be good choices. Regarding graphics cards for flight simulators, typically these aren't as important, you may be best off keeping that 1080Ti as I've heard nothing about any ray-tracing needs for FS2020.

 

[DrMrLordX]

DrMrLordX,

Thanks. Product Numbering systems these days seem somewhat complex/convoluted but my understanding is that Ryzen 2 (3000 series) is what is currently being sold and that Ryzen 3 (4000 series) is what's "coming next" (the one that this thread is about) and will already be released by this time next year. Does that sound right? I'm interpreting what you wrote as that...

Yeah. AMD's Zen-based lineup works thusly:

Zen (Summit Ridge) - Ryzen 1xxx
Zen+ (Pinnacle Ridge) - Ryzen 2xxx, though the low-end APU parts are actually Raven Ridge which is Zen.
Zen2 (Matisse) - Ryzen 3xxx, not counting the low-end parts which are actually Picasso which is Zen+.
Zen3 - Ryzen 4xxx

 

[soresu]

Yeah. AMD's Zen-based lineup works thusly:

Zen (Summit Ridge) - Ryzen 1xxx
Zen+ (Pinnacle Ridge) - Ryzen 2xxx, though the low-end APU parts are actually Raven Ridge which is Zen.
Zen2 (Matisse) - Ryzen 3xxx, not counting the low-end parts which are actually Picasso which is Zen+.
Zen3 - Ryzen 4xxx

I think Zen3 was named Vermeer on a roadmap, not that it matters a bit of course!

I think Dali may end up with a low end 3xxx or 4xxx number, still little info on it, less than Renoir in any case.

 

[DrMrLordX]

I think Zen3 was named Vermeer on a roadmap, not that it matters a bit of course!

Yeah my brain isn't thinking that far ahead.

I think Dali may end up with a low end 3xxx or 4xxx number, still little info on it, less than Renoir in any case.

Right, not much info on Dali out there. Regardless, OP @Caveman will not want Dali.

 

[NostaSeronx]

I think Dali may end up with a low end 3xxx or 4xxx number, still little info on it, less than Renoir in any case.

Right, not much info on Dali out there. Regardless, OP will not want Dali.

Dali was supposedly going to be a 7nm+ Zen3/RDNA2 budget APU. However, it might just be Picasso's Raven2 on 12LP+. There is some rumors that because it has a 128-bit MC, it might op for a new tapeout with a larger GPU.

RAVEN_A0 spawn:
Quad-core + up to 11 CU GCN + 128-bit IMC
RAVEN2_A0 spawn:
Dual-core + up to 3 CU GCN + 128-bit IMC
RAVEN1_F0 spawn:
Dual-core Zen++ (12LP+) + 6CU-8CU GCN + 128-bit IMC.
Dali from before the patch, rumored;
Dual-core Zen3 (7nm+) + 8 CU RDNA2(Super-SIMD?/Budget RT) + 128-bit IMC.

===
Also, I've been getting these "Game cores w/ gamecache" 17h-esque and "System cores w/ systemcache" Family 16h-esque rumors. Eight-cores of Zen + Sixteen-cores of Jaguar, with all system operations(AV(bitdefender)/Defrag(Windows Defrag)/Background browser/chat/etc) happening on Multitask-focused Jaguar cores, and all game(Doom Eternal/etc)/compute(F@H/Blender) running on Singletask-focused Zen cores. With near-100% usage of Jaguar CCD, not affecting performance of near-100% Zen CCD. No more single CCD chiplets being the theme; either all Zen "Compute focused", all Jag "Business focused", or one of each "Gamer focused".

Ryzen CPU => 2 Zen CCDs or 1 Zen CCD + 1 Jag CCD. => Ryzen 4900 being both Zen, Ryzen 4800 and below being Zen+Jag.
Athlon CPU => 2 Jag CCDs => Athlon 400 being both Jag. All of them are PRO.

Inverse of N1/E1 on threading, with AMD's N1-equiv with SMT and E1-equiv with no SMT. Mostly similar to the N1/E1 edge references in the CCD design.

 

[soresu]

Dali was supposedly going to be a 7nm+ Zen3/RDNA2 budget APU. However, it might just be Picasso's Raven2 on 12LP+. There is some rumors that because it has a 128-bit MC, it might op for a new tapeout with a larger GPU.

RAVEN_A0 spawn:
Quad-core + up to 11 CU GCN + 128-bit IMC
RAVEN2_A0 spawn:
Dual-core + up to 3 CU GCN + 128-bit IMC
RAVEN1_F0 spawn:
Dual-core Zen++ (12LP+) + 6CU-8CU GCN + 128-bit IMC.
Dali from before the patch, rumored;
Dual-core Zen3 (7nm+) + 8 CU RDNA2(Super-SIMD?/Budget RT) + 128-bit IMC.

===
Also, I've been getting these "Game cores w/ gamecache" 17h-esque and "System cores w/ systemcache" Family 16h-esque rumors. Eight-cores of Zen + Sixteen-cores of Jaguar, with all system operations(AV(bitdefender)/Defrag(Windows Defrag)/Background browser/chat/etc) happening on Multitask-focused Jaguar cores, and all game(Doom Eternal/etc)/compute(F@H/Blender) running on Singletask-focused Zen cores. With near-100% usage of Jaguar CCD, not affecting performance of near-100% Zen CCD. No more single CCD chiplets being the theme; either all Zen "Compute focused", all Jag "Business focused", or one of each "Gamer focused".

Ryzen CPU => 2 Zen CCDs or 1 Zen CCD + 1 Jag CCD. => Ryzen 4900 being both Zen, Ryzen 4800 and below being Zen+Jag.
Athlon CPU => 2 Jag CCDs => Athlon 400 being both Jag. All of them are PRO.

Inverse of N1/E1 on threading, with AMD's N1-equiv with SMT and E1-equiv with no SMT. Mostly similar to the N1/E1 edge references in the CCD design.

You can't mix Jag and Zen on the same CPU for a big little type of design.

The instruction set support is too different, no AVX2 in Jaguar at the very least.

Likewise the big ARM cores are constrained to the IS support of A55.

 

[NostaSeronx]

You can't mix Jag and Zen on the same CPU for a big little type of design.

The instruction set support is too different, no AVX2 in Jaguar at the very least.

Likewise the big ARM cores are constrained to the IS support of A55.

It falls under a slight improvement to this: https://docs.microsoft.com/en-us/windows/win32/procthread/cpu-sets

One Windows Kernel

Windows is one of the most versatile and flexible operating systems out there, running on a variety of machine architectures and available in multiple SKUs. It currently supports x86, x64, ARM and ARM64 architectures. Windows used to support Itanium, PowerPC, DEC Alpha, and MIPS (wiki entry). In...

techcommunity.microsoft.com

"By app intent, I mean Windows tries to provide a quality of service for apps by tracking threads which are running in the foreground (or starved of CPU) and ensuring those threads always run on the big core. Whereas the background tasks, services, and other ancillary threads in the system run on the little cores. (As an aside, you can also programmatically mark your thread as unimportant which will make it run on the LITTLE core.)"

///
With LKF, there is no reason to not have big.Little heterogeneous ISA/perf cores. (sunnycove with AVX512 and tremont with SSE4.x)
--
Even though I typed Jaguar, the LP core might be a scaled-down refactor of Zen1 on 7nm+ and the HP core might be a scaled-up refactor of Zen2 on 7nm+. ¯\_(ツ)_/¯

Scaled-down examples:
1. 192 retire queue(SMT2) -> 112 retire queue(No-SMT)
2. 320B pick buffer(SMT2) -> 160B pick buffer(No-SMT)
3. Same ALUs/AGUs but with smaller schedulers and less physical register files(A guess: 168-entry to 92-entry or something with no SMT)
4. Smaller FPU with 1x 256-bit FPM + 1x 256-bit FPA(No-SMT/FMA bridge present)
=> It is suppose to be Jaguar looking.

 

[soresu]

It falls under a slight improvement to this: https://docs.microsoft.com/en-us/windows/win32/procthread/cpu-sets

One Windows Kernel

Windows is one of the most versatile and flexible operating systems out there, running on a variety of machine architectures and available in multiple SKUs. It currently supports x86, x64, ARM and ARM64 architectures. Windows used to support Itanium, PowerPC, DEC Alpha, and MIPS (wiki entry). In...

techcommunity.microsoft.com

"By app intent, I mean Windows tries to provide a quality of service for apps by tracking threads which are running in the foreground (or starved of CPU) and ensuring those threads always run on the big core. Whereas the background tasks, services, and other ancillary threads in the system run on the little cores. (As an aside, you can also programmatically mark your thread as unimportant which will make it run on the LITTLE core.)"

///
With LKF, there is no reason to not have big.Little heterogeneous ISA/perf cores. (sunnycove with AVX512 and tremont with SSE4.x)
--
Even though I typed Jaguar, the LP core might be a scaled-down refactor of Zen1 on 7nm+ and the HP core might be a scaled-up refactor of Zen2 on 7nm+. ¯\_(ツ)_/¯

Scaled-down examples:
1. 192 retire queue(SMT2) -> 112 retire queue(No-SMT)
2. 320B pick buffer(SMT2) -> 160B pick buffer(No-SMT)
3. Same ALUs/AGUs but with smaller schedulers and less physical register files(A guess: 168-entry to 92-entry or something with no SMT)
4. Smaller FPU with 1x 256-bit FPM + 1x 256-bit FPA(No-SMT/FMA bridge present)
=> It is suppose to be Jaguar looking.

The point is regardless of uArch, the IS support across all cores must be uniform - otherwise you can't pass a thread/process from low power core to high power core or vice versa with any degree of certainty that all code will run (even if it runs slowly like AVX on Jaguar, or AVX2 on Znver1).

 

[NostaSeronx]

The point is regardless of uArch, the IS support across all cores must be uniform - otherwise you can't pass a thread/process from low power core to high power core or vice versa with any degree of certainty that all code will run (even if it runs slowly like AVX on Jaguar, or AVX2 on Znver1).

AMD isn't Intel, so I doubt they will impair their cores. However, SSE to AVX and AVX to SSE is easy on Intel, so it should be easy on AMD. Anything that runs on Sunnycove can also run Tremont, do to pre-compiled/runtime/jit trickery and the fact that lots of programs are still SSE.

AVX/AVX2/(AVX3) are 128-bit, 256-bit, (512-bit). When you say AVX on Jaguar and AVX2 on Zen. You should really specify that you are talking about 256-bit. Since, AVX doesn't run slowly on Jaguar, nor does AVX2 run slowly on Zen. Only the 256-bit components do, however most code is still 128-bit.

 

[jpiniero]

The point is regardless of uArch, the IS support across all cores must be uniform - otherwise you can't pass a thread/process from low power core to high power core or vice versa with any degree of certainty that all code will run (even if it runs slowly like AVX on Jaguar, or AVX2 on Znver1).

That's how Lakefield works. Intel did add a fast "Read Processor ID" instruction to help but I imagine there's also something like being able to send the process to the big core if a AVX instruction is run.

 

[Abwx]

GlobalFoundries Unveils 12LP+ Technology: Massive Performance & Power Improvements

www.anandtech.com

Will likely be used for Zen 3 I/O chip....

 

[krumme]

GlobalFoundries Unveils 12LP+ Technology: Massive Performance & Power Improvements

www.anandtech.com

Will likely be used for Zen 3 I/O chip....

Zen4 I assume because 2021 mass production?

 

[Abwx]

2021 is for news designs, AMD s I/O is already designed athough there will surely an overhaul for RAM channels FI.

This should cut by 2 the power drain of Epyc 2 14LP based I/O, besides Zen 3 is more relevant for early 2021, at this point they need to better amortize each iteration, and if sucessive gens are released too early there will be constantly a wait effect...

 

[Ajay]

2021 is for news designs, AMD s I/O is already designed although there will surely an overhaul for RAM channels FI.

This should cut by 2 the power drain of Epyc 2 14LP based I/O, besides Zen 3 is more relevant for early 2021, at this point they need to better amortize each iteration, and if successive gens are released too early there will be constantly a wait effect...

There is a new PDK and there will be substantial design efforts required by customers to produce products for the new process according to the article. I expect that AMD will be one of the customers taping out in 2h2020:

GlobalFoundries expects its customers to tape out the first 12LP+ SoCs sometimes in the second half of 2020 and produce them in volume in 2021.

I haven't heard anything about Zen3 tapeouts yet, so I have not idea when CPU products are actual due to arrive however.

 

[NostaSeronx]

There is a new PDK and there will be substantial design efforts required by customers to produce products for the new process according to the article.

No substantial redesign effort just a re-tapeout: "While the Flex Logix validation chip was fabricated in GF’s 14LPP, the GDS is also compatible with GF’s 12LP and 12LP+ because the design was done with GF standard cells and register files."

Anything on 14LPP can be on 12LP which can also be on 12LP+. GlobalFoundries timelines are pretty stupid...

GLOBALFOUNDRIES Introduces New 12nm FinFET Technology for High-Performance Applications

New 12LP technology offers density and performance improvement over current generationPlatform features enhancements for next-gen automotive electronics and RF/analog applications

www.globalfoundries.com

Sep 20, 2017 first 12LP processors => April 19, 2018

GLOBALFOUNDRIES Introduces 12LP+ FinFET Solution for Cloud and Edge AI Applications

Innovative solution based on GF’s most advanced FinFET platform offers best-in-class performance, key new features to address evolving AI requirements, compelling economics and industry-leading physical IP from Arm

www.globalfoundries.com

Sep 24, 2019 then first 12LP+ processors => April 23, 2020.

 

[Abwx]

There is a new PDK and there will be substantial design efforts required by customers to produce products for the new process according to the article. I expect that AMD will be one of the customers taping out in 2h2020:


I haven't heard anything about Zen3 tapeouts yet, so I have not idea when CPU products are actual due to arrive however.

If they want to fullfill the WSA in 2021/22 without having to buy sub performing silicon dunno what they can do else, using 12LP for next Epyc I/O would be a mistake given the characteristics of this 12LP+.

Another advantage would be uniformisation of DT and servers I/O designs wich are crrently using two different processes, also it is relevant for a 512SP based Picasso as low cost solution.

 

[Ajay]

I don't think we will be seeing unified DT & server IO chips anytime soon. Is this a stated goal by AMD?

 

[Abwx]

I don't think we will be seeing unified DT & server IO chips anytime soon. Is this a stated goal by AMD?

Unified libraries and layouts of the common parts, FI the IMC cicuitry and other IFs, USB and so on.