Speculation: Ryzen 4000 series/Zen 3

[NostaSeronx]

I'm trying to work my head around the pros and cons of running Vermeer on 5nm while running Milan on 7nm+. The chiplets in the Epycs are top cream, so they may not totally benefit from a shrink. IIRC one of TSMC's 7nm+ variants supposedly brings in 10% lower energy use or around there. That may be useful especially if AMD can also improve clocks for Epyc. Makes sense to run Vermeer on 5nm since they'll have a better idea but as you said it's still a weird situation because they're running multiple nodes of chiplets they may not actually be able to fully bin. Unless they go 5nm everything?

Everything should be available on 5nm.
I believe AMD's N5 access is a lot more custom.
44~57Cx support and 28~57Mx support. Thus allowing 7nm/7nm+ to be retaped out on 5nm, with 6nm only being a cost-effective subset supporting only 7nm DUV.

Zen3 for N5 is a retapeout of N7, while Zen4 for N5 is a new tapeout not derivied from N7.

I thought the TSMC AZ plant was to supply US contractors who worked in the defense industry alongside the armed forces? That's the common argument because it was rumored it was for Intel, but it didn't make sense. It's not a big plant either from what I've been told.

It could be used that way, but it is mostly for US customers worried about you know who across the Taiwan strait.

 

[Martimus]

I don't understand the sudden belief that Zen 3 will be on 5nm. AMD has stated multiple times that Zen 3 will be on 7nm, and if they designed for the N7 node, then they can't easily switch to the N5 node since the N5 node uses EUV in multiple areas and requires far different design rules than N7. N6 is possible since it uses most of the same design rules as N7, but I would take AMD at their word and believe Zen 3 will be produced on the N7 node. They don't exactly have any reason to lie about that.

 

[NostaSeronx]

N5 node uses EUV in multiple areas and requires far different design rules than N7.

Usage of EUV doesn't mean different design rules. It means different masks only.

If the standard-custom library cells support N5 doing N7 then it is 100% compatible. The difference is buying ~90 masks or ~70 masks.

 

[Martimus]

Usage of EUV doesn't mean different design rules. It means different masks only.

If the standard-custom library cells support N5 doing N7 then it is 100% compatible.

Everything I've read about N5 is that it requires pretty substantial changes to design rules, which is the primary reason they created the N6 node. The N6 node is an easy upgrade to N7 for customers that don't want to put in the extra work optimizing for N5.

 

[NostaSeronx]

Everything I've read about N5 is that it requires pretty substantial changes to design rules, which is the primary reason they created the N6 node. The N6 node is an easy upgrade to N7 for customers that don't want to put in the extra work optimizing for N5.

Scaled/smart scaled designs have different designs, thus different rules.

N7 57Cx/40-57Mx min, N7+ 57Cx/36Mx min => N5 44Cx/28Mx min. So long as one doesn't use the scaling factor then no design rules are added.

N5 w/ 57Cx/36Mx or 57Cx/up to 57Mx => Same design rules, flow, EDA readiness as N7/N7+.

They did this before on the PDSOI nodes. 45nm/32nm re-used 65nm rules on long channels to reduce costs/power. AMD has to maintain Fmax/Fsustained growth going onwards this means usage of newer transistors/nodes with older design rules.

 

[A///]

I don't understand the sudden belief that Zen 3 will be on 5nm. AMD has stated multiple times that Zen 3 will be on 7nm, and if they designed for the N7 node, then they can't easily switch to the N5 node since the N5 node uses EUV in multiple areas and requires far different design rules than N7. N6 is possible since it uses most of the same design rules as N7, but I would take AMD at their word and believe Zen 3 will be produced on the N7 node. They don't exactly have any reason to lie about that.

It's not a sudden belief. It's just idle chit chat and theory. I don't know if I'm truly using this phrase correctly, but it could be AMD's October surprise, no pun intended. Their "gotcha" if you will, but even then it just complicates everything down the line. At best I want to believe in the Ryzen 5000 namesake with the 4000 being skipped over to stop all the confusion.

 

[Thunder 57]

It's not a sudden belief. It's just idle chit chat and theory. I don't know if I'm truly using this phrase correctly, but it could be AMD's October surprise, no pun intended. Their "gotcha" if you will, but even then it just complicates everything down the line.

You got the phrase right. I wouldn't expect Nostra to be right though. I don't know if it's happened yet.

At best I want to believe in the Ryzen 5000 namesake with the 4000 being skipped over to stop all the confusion.

I very much agree. I don't have much faith in AMD's marketing people though.

 

[A///]

You got the phrase right. I wouldn't expect Nostra to be right though. I don't know if it's happened yet.



I very much agree. I don't have much faith in AMD's marketing people though.

Didn't AMD make people in their marketing department redundant for some of their stunts in the past? I'd hope they thought of that only because it gets confusing having to explain it to non computer folk, not to mention it not being easy for consumers to know what they're getting.

 

[DrMrLordX]

AMD has stated multiple times that Zen 3 will be on 7nm, and if they designed for the N7 node, then they can't easily switch to the N5 node since the N5 node uses EUV in multiple areas and requires far different design rules than N7.

That would be relevant if Zen3 were on N7. It's on N7+.

 

[Martimus]

That would be relevant if Zen3 were on N7. It's on N7+.

When AMD was asked to specify which enhanced N7 node (N7+ or N7P) they answered in a way that made me think they were using the non EUV node. Of course I don't know exactly what they are doing, but it seems highly unlikely that AMD would build at risk on a new process node when they don't need to. I would expect them to start on the N5 node next year when yields, prices, and availability are better.

 

[trexfromouterspace]

The "Zen 3 is actually releasing on N5" rumor was always dumb, and it's even dumber now that Nosta's parroting it.

Go back to talking about how amazing Intel's 7nm yields are you redacted.

Do not insult other posters.

Iron Woode
Super moderator

 

[LightningZ71]

A lot of this is getting bogged down in the ever changing definitions that TSMC has given to their node names. N7+ is not the same as AMD's "improved N7" node statement. N7+ had different design rules than N7 and wasn't design compatible. N7 was to flow into N6, with a later added "improved N7" node in between. N7P was to flow into N5. Then, it came to light that there was an N5P or + node that was done with AMD in mind, which may or may not be a lead in node for N3 as well.

I don't doubt that AMD has worked with TSMC to have a Zen3 floorplan and design for N7 improved and N5p. It wouldn't shock me if AMD produced EPYC and desktop ryzen Chiplets for Zen3 on improved N7 and used N5p or N6 for Cezanne or a following product. I see huge advantages for AMD using N6 for Cezanne instead of N7 improved. Cezanne, using the larger Zen3 cores and using the newer unified L3 CCX design, will be a larger floorplan (more transistors to pack in). That would require the die to grow if it stayed on N7. It's got to get some sort of shrink to keep its yield per wafer numbers up enough to make sense in the market. N6 would answer a lot of that. N6 would allow Vega to move forward as well since it's rules compatible enough to allow the 7nm VEGA layout to move with the Zen3 cores.

This is all idle speculation and I have no actual information. It just seems really odd to me that AMD wouldn't use N6 for Cezanne if it is really rules compatible and is also available as a production quality node.

 

[pike55]

AMD clarified this some time ago.

AMD never said ZEN3 will only be on 7nm. Also this was before the Huawei decision, which is the whole basis for the possibility to switch to 5nm earlier. (Together with the growing demand for 7nm capacity (Nvidia, Intel ...))

Theory:

1. AMD needs a reliable Server CPU schedule, therefore they surely have a 7nm ZEN3 CPU chiplet version ready which they can (not must) release as Server andor TR andor Desktop. Original plans were to release all of that.
   
   
2. AMD has also been working with TSMC on a (customizted) 5nm process for a long time. Therefore they must have a 5nm design for the test runs. (Maybe they used VEGA and some ZENx for these test runs since these were known and ready when they startet this test work).
   
   
3. AMD is preparing a 5nm APU with ZEN3 for quite a while also (original plans for Rembrandt) and probably originally planned this as the first 5nm product. Since this (APUs) is where the advantages of 5nm matter most. (And AMD is ahead in Server and Desktop CPUs anyway.)
   
   
4. Now (a few months ago) suddenly TSMC calls Lisa "Huawei is out, do you want a big chunk of 5nm capacity and move ahead from 7nm earlier?" - "YES".
   AMD has the decision what to produce on 5nm.
   
   
5. Design for ZEN3 on 5nm was already in preparation for Rembrandt (see 3.) And Vega was ready from the original 5nm test runs (see 2.)
   Put both together and you get Cezanne.
   Using Vega for that always seemed odd, but in this scenario it would make a lot of sense since it can be brought into production quickly. (The design for RDNA2/3 on 5nm is not ready yet and Navi was never planned for 5nm.)
   
   
6. ZEN3 CPU chiplets are not hard to design either (when most of the work is already done, see above).
   Same question here as in 1. - Which products to produce from 5nm ZEN3 CPU chiplets: Server andor TR andor Desktop?

No doubt the original plan for AMD was ZEN3 chiplets on 7nm (enh.) but if the theory of 5nm capacity available is correct they now have a lot of options.
Surely they can use all their 7nm capacity for consoles + GPUs + existing CPU and APUs alone.

They could produce ZEN3 CPU chiplets on 7nm and 5nm, and assign them to Server, TR and Desktop products depending on the capacity and demand.
Probably 7nm for Server. This would be the safe option to be reliable in the server space. (However, if a huge customer asks for a 5nm version AMD woudn't say no either.)

If 5nm works reliably enough and capacity is there, they might decide to go for 5nm for all products as well.
TSMC could trade: Give AMD more 5nm capacity and get back some 7nm capacity in return which other customers there desperately need. Would AMD say no to such a trade? (Especially if the price is right.)

(Edit) PS: The many options that AMD has if and how they could use 7nm andor 5nm for ZEN3 would also explain why they are not releasing any information yet. It may not be decided yet. And they could even change that after launch.(Hopefully with different product names.)

 

[pike55]

but it seems highly unlikely that AMD would build at risk on a new process node

N5 is being used by Apple since 2? years now. It's well known and understood.

when they don't need to.

They don't need to, but when you can get ahead of Intel significantly (especially in APUs) why throw away that possibility?

I would expect them to start on the N5 node next year when yields, prices, and availability are better.

The yields are high on 5nm, that is part of the rumors if you haven't noticed.
Prices being low and availability being high (for AMD) is the whole point and basis of the rumor in the first place.

Edit: 1st paragraph is wrong memory from me.

 

[jpiniero]

N5 is being used by Apple since 2? years now. It's well known and understood.

TSMC 5 nm HVM was in April. Does say TSMC expects a quick ramp but there are no products on the market yet using it. Apple's first product is the 2020 iPhone presumably.

 

[pike55]

TSMC 5 nm HVM was in April. Does say TSMC expects a quick ramp but there are no products on the market yet using it. Apple's first product is the 2020 iPhone presumably.

I had a false memory there on 5nm, sorry.
I do remember hearing that yields looked quite good for Apple for that HVM in April?

 

[Thunder 57]

AMD never said ZEN3 will only be on 7nm. Also this was before the Huawei decision, which is the whole basis for the possibility to switch to 5nm earlier. (Together with the growing demand for 7nm capacity (Nvidia, Intel ...))

Theory:

1. AMD needs a reliable Server CPU schedule, therefore they surely have a 7nm ZEN3 CPU chiplet version ready which they can (not must) release as Server andor TR andor Desktop. Original plans were to release all of that.
   
   
2. AMD has also been working with TSMC on a (customizted) 5nm process for a long time. Therefore they must have a 5nm design for the test runs. (Maybe they used VEGA and some ZENx for these test runs since these were known and ready when they startet this test work).
   
   
3. AMD is preparing a 5nm APU with ZEN3 for quite a while also (original plans for Rembrandt) and probably originally planned this as the first 5nm product. Since this (APUs) is where the advantages of 5nm matter most. (And AMD is ahead in Server and Desktop CPUs anyway.)
   
   
4. Now (a few months ago) suddenly TSMC calls Lisa "Huawei is out, do you want a big chunk of 5nm capacity and move ahead from 7nm earlier?" - "YES".
   AMD has the decision what to produce on 5nm.
   
   
5. Design for ZEN3 on 5nm was already in preparation for Rembrandt (see 3.) And Vega was ready from the original 5nm test runs (see 2.)
   Put both together and you get Cezanne.
   Using Vega for that always seemed odd, but in this scenario it would make a lot of sense since it can be brought into production quickly. (The design for RDNA2/3 on 5nm is not ready yet and Navi was never planned for 5nm.)
   
   
6. ZEN3 CPU chiplets are not hard to design either (when most of the work is already done, see above).
   Same question here as in 1. - Which products to produce from 5nm ZEN3 CPU chiplets: Server andor TR andor Desktop?

No doubt the original plan for AMD was ZEN3 chiplets on 7nm (enh.) but if the theory of 5nm capacity available is correct they now have a lot of options.
Surely they can use all their 7nm capacity for consoles + GPUs + existing CPU and APUs alone.

They could produce ZEN3 CPU chiplets on 7nm and 5nm, and assign them to Server, TR and Desktop products depending on the capacity and demand.
Probably 7nm for Server. This would be the safe option to be reliable in the server space. (However, if a huge customer asks for a 5nm version AMD woudn't say no either.)

If 5nm works reliably enough and capacity is there, they might decide to go for 5nm for all products as well.
TSMC could trade: Give AMD more 5nm capacity and get back some 7nm capacity in return which other customers there desperately need. Would AMD say no to such a trade? (Especially if the price is right.)

(Edit) PS: The many options that AMD has if and how they could use 7nm andor 5nm for ZEN3 would also explain why they are not releasing any information yet. It may not be decided yet. And they could even change that after launch.(Hopefully with different product names.)

Yea, sounds about as likely as getting struck by lightning while a shark is tearing you apart. That's after surviving a plane crash in the ocean, mind you.

 

[NostaSeronx]

I don't doubt that AMD has worked with TSMC to have a Zen3 floorplan and design for N7 improved and N5p.

The actual info given back when I said 7nm+ problems long ago:
K18.2 was on N7 and is a derivative part of K18.1
K19.x was never on N7 and isn't a derivative part of K18.1/K18.2.

Family 19h was always planned for 5nm.

The family introduced with Zen5 is targeting 3nm / 2nm at TSMC as extra info. Most of this was decided shortly after GloFo said nah about 7LP/3LP since 5LP was already canned. Family 19h fully switched to TSMC 5nm after 5LP was canned earlier(than 7nm/3nm being also canned).

May 31, 2018 -> As it appears, in a bid to provide more tangible advantages to its customers and not to invest in short-lasting nodes, the company is mulling skipping 5 nm manufacturing technology like it did with the 10 nm fabrication process. [They canned it in the docs => 5LP -> 3LP way before that, no mulling whatsoever]
August 27, 2018 -> The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. [Also, includes 3LP]
//Which is why AMD started working with TSMC on 5nm since 2018. With the most of the work being finished after April 3, 2019 and rest of 2019: Earlier this week TSMC announced that their 5-nanometer process technology has entered risk production. 5 nm PDKs are now available for production design and design components and rules have been delivered to their Open Innovation Platform (OIP), ready for customer designs.

Zen3 on N7 technically can only be K18.2. Since, Fam19h via the cores team is N5.

Fam 18h => increased vector width from 17h and misc/etc improvements per generation. (Native AVX256 -> Native AVX512)
Fam 19h => increased clock speeds and uniformity in execution units per generation. (No native AVX512 planned, the word is also no native AVX256 either)

 

[A///]

I wonder if some of the delay has been a result of AMD acutely aware of the current PC component shortages going on due to you know what and people buying products en-masse. It would effect SIs and OEMs too if you think about it. Thought shortages seem to have resolved just over a month ago.

I myself was finally able to buy a proper webcam from Logitech last night.

 

[DrMrLordX]

When AMD was asked to specify which enhanced N7 node (N7+ or N7P) they answered in a way that made me think they were using the non EUV node. Of course I don't know exactly what they are doing, but it seems highly unlikely that AMD would build at risk on a new process node when they don't need to. I would expect them to start on the N5 node next year when yields, prices, and availability are better.

https://twitter.com/x/status/1279873180862230528

N7+ confirmed, thanks to @Antey for originally pasting the link (earlier in this thread no less).

Zen3 will not be N7, N7P, or N6.

 

[NostaSeronx]

N7+ confirmed

HiSilicon Kirin 1000 / AMD Cezanne

If Kirin 1000/1020/1100/1120 are N5
If Apple A14/A14X/A14_ are N5
Then, atleast Cezanne is N5 and will potentially paper launch with the above.
=> "As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”

5nm started with GPUs, then got into CPUs, and is finally on the APU.
GPU -> CPU -> APU

Is GN-B0/VMR-B0 7nm still?

The only case of new steppings pointing towards to a newer node is in the Thunderbird/Hammer/Greyhound days.
A -> B (180nm - 130nm)
C -> D/E (130nm - 90nm)
F -> G (90nm - 65nm)
B -> C (65nm - 45nm)

Memo for AMD Zen Family CPU/APU Stepping. : Komachi_ENSAKA

I'm Not Detective. I'm just Seeker.

www.reddit.com

~20,000 wpm for N5-class wafers in 2020
~30,000 wpm for N5P-class wafers in 2021
Phase 1&2 => 40K+40K for 2020.
Phase 3 => +40K for 2021.
I believe those numbers are pretty low on a modern-sense, so capacity might actually be higher.

 

[Martimus]

https://twitter.com/x/status/1279873180862230528

N7+ confirmed, thanks to @Antey for originally pasting the link (earlier in this thread no less).

Zen3 will not be N7, N7P, or N6.

Who is ZimogoretS, and why do you trust them implicitly?

EDIT: I realize now that probably came out aggressively. Thank you for the additional information, but I never assume that any non official source is correct, especially without any explanation for what the information means, or where it came from. I just wanted to know some background on who this person was to better understand why they are posting random manufacturing information.

 

[lobz]

Reading this thread is a lot of fun, first a whole page worth of 2 guys arguing about semantics of previous posts, and then somebody thought it was a good idea to seriously debate Nosta's hallucinations 😂

 

[DrMrLordX]

Who is ZimogoretS, and why do you trust them implicitly?

https://twitter.com/zimogorets

Judge for yourself.

 

[Kenmitch]

Reading this thread is a lot of fun, first a whole page worth of 2 guys arguing about semantics of previous posts, and then somebody thought it was a good idea to seriously debate Nosta's hallucinations 😂

It's a speculation thread. The normal rules of logic don't apply. They might sound silly, but....

spec·u·la·tion
/ˌspekyəˈlāSH(ə)n/
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noun

1. the forming of a theory or conjecture without firm evidence.

Sometimes a silly speculative comment could lead to the missing link required for advancement of the tech. Not saying it'll happen, but it's not beyond the realm of possibility.