Speculation: Ryzen 3000 series

[Spartak]

Can you expand upon this please?
What is it about the demo itself that tells you that they were running high frequencies, and that this necessitates lower clocks on a 16c SKU?
I'm seeing an ES sample that would have been running high voltages for stability, and not necessarily high clocks. In fact, anything 4.5GHz+ would represent IPC regression, which is highly unlikely.
Beyond that, we know that IF consumes huge chunks of power, and if we model that to the actual power usage for the demo, we can see that the 8c chiplet is likely not consuming much power at all. In fact, another 8c chiplet is unlikely to add more than 20-30w at the same frequency as in the demo. The 16c SKUs are supposedly 125w and 135w.
I'm fairly confident that AMD were sandbagging. Perhaps not by a massive amount, but by enough to get the message across.

See the anandtech article that TDP range will remain the same as ryzen2. So no 125-135w SKUs.

The 4.5 Ghz statement from sources wouldn't be a CB15 regression. The 2700x gets 1750 at 4.3 so it'd still be a 12% IPC improvement. Based upon statements in this thread from a few posters the changes to the FPU wouldn't have much of an impact on CB15 anyway so average IPC uplift would still be higher.

 

[PotatoWithEarsOnSide]

It gets 1900 at 4.3GHz.

 

[PotatoWithEarsOnSide]

Anyway, if it is 75w for 8c at 4.5GHz, and the IF takes up 45w of that, then there's still 30w for each 8c chiplet.
Zen+ IF used 55w, so....

 

[Spartak]

Not according to anandtech which has it at 1754. Those scores must have been on fast memory maybe? But the ES was running slow memory so I think 1754 is the proper baseline.

 

[Spartak]

Anyway, if it is 75w for 8c at 4.5GHz, and the IF takes up 45w of that, then there's still 30w for each 8c chiplet.
Zen+ IF used 55w, so....

Two chiplets would also mean double the IF power usage.

And would like to see from where you got those huge numbers...sounds completely off to me.

 

[IRobot23]

Interesting how they have stated Ryzen3 will have the same TDP range as Ryzen2.

How can they have 16-cores with a 14nm IO fit inside 105W TDP, unless the ES was already running at pretty high frequency? Rumors had the ES running at ~4.5GHz, so a 16-core running at ~4GHz all core *might* fit that TDP.

Together with there not being any G versions the AdoredTV leak is completely out of the window by now.

ES cannot run at 4,5GHz

Who ever claim that did not think trough it.
R7 2700X 4,5-4,6GHz ~ i9 9900K 4,7GHz in MT CB R15

 

[PotatoWithEarsOnSide]

Two chiplets would also mean double the IF power usage.

If you're going to quote Anandtech figures as your justification for one wrong number, perhaps you should also quote Anandtech's view on IF scaling with core count. FYI, it doesn't; quite the contrary...IF is barely consuming any more power as core counts increase. This one of the main reasons why AMD are able to scale core count so easily.
Anandtech even produced graphs on it, and these were reproduced recently after I brought up this exact thing in another conversation.

Should I dismiss all of your post in the way you dismissed Adoredtv information just because your source is giving you dodgy info?

 

[exquisitechar]

Not according to anandtech which has it at 1754. Those scores must have been on fast memory maybe? But the ES was running slow memory so I think 1754 is the proper baseline.

Hmm, I checked the review and it's 1792 at stock.

+1 IFOP is used for 16c/12c, so yeah, that'll be higher power for load?

 

[IRobot23]

I want to know clock for IF 2, IMC capabilities, and overall dram latency

 

[Spartak]

If you're going to quote Anandtech figures as your justification for one wrong number, perhaps you should also quote Anandtech's view on IF scaling with core count. FYI, it doesn't; quite the contrary...IF is barely consuming any more power as core counts increase. This one of the main reasons why AMD are able to scale core count so easily.
Anandtech even produced graphs on it, and these were reproduced recently after I brought up this exact thing in another conversation.

Should I dismiss all of your post in the way you dismissed Adoredtv information just because your source is giving you dodgy info?

I think you are confusing a few things here. First of all its not MY source stating that 4.5 GHZ, and I never stated it as fact.

Second, the TDP and GPU statements that contradict AdoredTV's list are statements from AMD and published by anandtech.

So if you feel the need to get snarky regarding IF power usage (haven't seen that article but I'll take your word for it) you got some egg on your face too.

 

[Mopetar]

ES cannot run at 4,5GHz

Edit: I think I misunderstood what the poster was saying. Post below clarifies things.

Any reason it can't? We don't really know what the TSMC 7nm node is capable of or exactly how far along AMD is with finalizing Zen 2. They also had the opportunity to pick the very best silicon for this demonstration, so it's not unreasonable to imagine such a case.

The alternative to assuming a high clock speed like that is that AMD was able to achieve an utterly stupid amount of improvement in IPC, which is far less likely than the new process giving them a solid bump on top of using a top 1% chip capable of hitting high clock speeds even though it's not production silicon yet.

The only other explanation is that their SMT is even more improved which allows them to see even better MT performance compared to Intel, but I'm not sure how likely that is and most people were genuinely surprised Ryzen was as good as it was to begin with, never mind being better than Hyper-Threading.

 

[PotatoWithEarsOnSide]

If you are stating it as the basis for your figures then it is your source. Same goes for your incorrect Anandtech CB score at 4.3GHz for the 2700x.
Im telling you categorically that the score should be ~1900.
Im also telling you that Zen+ already provided better clock for clock IPC than the 9900K in CB R15 MT, which cannot be the case if 1754 is the 4.3GHz score for the 2700x. Hence why 4.5GHz+ has to be regression.
My own personal calculations have been based upon the more widely held view of 9-13% IPC gains for Zen 2 over Zen+, which leads to 4.1-4.3GHz for that ES demo.
I'm also telling you that ES Demos in a live setting will be running high voltages in order to run stable; you don't want the damned thing to crash.
If I can find the link to IF stuff then I will share it. I know you aren't questioning it, but it is still worth a read.

 

[IRobot23]

Any reason it can't? We don't really know what the TSMC 7nm node is capable of or exactly how far along AMD is with finalizing Zen 2. They also had the opportunity to pick the very best silicon for this demonstration, so it's not unreasonable to imagine such a case.

The alternative to assuming a high clock speed like that is that AMD was able to achieve an utterly stupid amount of improvement in IPC, which is far less likely than the new process giving them a solid bump on top of using a top 1% chip capable of hitting high clock speeds even though it's not production silicon yet.

The only other explanation is that their SMT is even more improved which allows them to see even better MT performance compared to Intel, but I'm not sure how likely that is and most people were genuinely surprised Ryzen was as good as it was to begin with, never mind being better than Hyper-Threading.

Let me correct my self. ES sample did not run at 4,5GHz all core. If it did then IPC = ZEN+
It had to run between 4-4.2GHz unless they even improved IPV even further

 

[exquisitechar]

If I can find the link to IF stuff then I will share it. I know you aren't questioning it, but it is still worth a read.

Is it this?

 

[PotatoWithEarsOnSide]

Any reason it can't? We don't really know what the TSMC 7nm node is capable of or exactly how far along AMD is with finalizing Zen 2. They also had the opportunity to pick the very best silicon for this demonstration, so it's not unreasonable to imagine such a case.

The alternative to assuming a high clock speed like that is that AMD was able to achieve an utterly stupid amount of improvement in IPC, which is far less likely than the new process giving them a solid bump on top of using a top 1% chip capable of hitting high clock speeds even though it's not production silicon yet.

The only other explanation is that their SMT is even more improved which allows them to see even better MT performance compared to Intel, but I'm not sure how likely that is and most people were genuinely surprised Ryzen was as good as it was to begin with, never mind being better than Hyper-Threading.

Logic says that it cannot have done. It would represent IPC regression.

 

[PotatoWithEarsOnSide]

Is it this?

Looks like it, yes.
There was also a similar article by another site but I don't recall which one.
The main takeaway was that whilst IF power draw does increase, it doesn't increase anywhere near 1:1 with cores, and it also appears to plateau. We also know that IF is the reason that Ryzen is a power hog when idling; the IF doesn't idle even when the cores do.

 

[Spartak]

If you are stating it as the basis for your figures then it is your source. Same goes for your incorrect Anandtech CB score at 4.3GHz for the 2700x.
Im telling you categorically that the score should be ~1900.
Im also telling you that Zen+ already provided better clock for clock IPC than the 9900K in CB R15 MT, which cannot be the case if 1754 is the 4.3GHz score for the 2700x. Hence why 4.5GHz+ has to be regression.
My own personal calculations have been based upon the more widely held view of 9-13% IPC gains for Zen 2 over Zen+, which leads to 4.1-4.3GHz for that ES demo.
I'm also telling you that ES Demos in a live setting will be running high voltages in order to run stable; you don't want the damned thing to crash.
If I can find the link to IF stuff then I will share it. I know you aren't questioning it, but it is still worth a read.

Anandtech has two scores for it, 1754 and 1792. So again, have these 1900 scores been reached with faster memory? If so the 1754 is still the proper baseline for an apples to apples comparison.

I also havent seen your response to this anandtech article. It pretty much buries the AdoredTV leaks.

I think the 4.5GHz source was mentioned in a recent video by UFD or Hardware Unboxed, not sure.

 

[Abwx]

Beyond that, we know that IF consumes huge chunks of power, and if we model that to the actual power usage for the demo, we can see that the 8c chiplet is likely not consuming much power at all. In fact, another 8c chiplet is unlikely to add more than 20-30w at the same frequency as in the demo. The 16c SKUs are supposedly 125w and 135w.
I'm fairly confident that AMD were sandbagging. Perhaps not by a massive amount, but by enough to get the message across.

Power being about 65W, the CPUs chiplet should be at 45-50W and the I/O chip at 20-15W, wich is the consumed power in Pinnacle Ridge I/O.

They can release either a 95W 8C at 15% higher frequency than the displayed ES, and/or a 115-125W 16C at same frequency than said ES.

We don't really know what the TSMC 7nm node is capable of or exactly how far along AMD is with finalizing Zen 2.

We know, 25% higher frequency at same power according to Mark Papermaster, and that s at 2GHz, assuming it scale as good up to 4.5GHz this would imply that the comparison use 65W at 3.6Ghz, wich is obviously not the case looking at the power of the R7 1700 and 2700, both 65W chips and comparable to the ES TDP wise.

If the comparison is SR then the ES was working at 3.8-3.9GHz, if it s PN then it was at 4GHz.

 

[Mopetar]

Logic says that it cannot have done. It would represent IPC regression.

I thought he meant that it couldn't hit those speeds. I'm assuming that AMD left clock speed on the table since they said that they weren't at final clocks and it's pretty obvious from the power draw that there's still plenty of headroom to throw more power at the chip. It seems unreasonable to assume that Zen 2 would top out where it did.

 

[PotatoWithEarsOnSide]

Anandtech has two scores for it, 1754 and 1792. So again, have these 1900 scores been reached with faster memory? If so the 1754 is still the proper baseline for an apples to apples comparison.

I also havent seen your response to this anandtech article. It pretty much buries the AdoredTV leaks.

I think the 4.5GHz source was mentioned in a recent video by UFD or Hardware Unboxed, not sure.

Can you have the same TDP range for a core count number that never previously existed? Either way, the 2700x runs above its TDP by around 10-15w.

Anyway,back to that IF link. Check out the 2950x; 16c Threadripper. IF consuming 33w at 1 core load, 45w at 16c load. It's the most directly comparable SKU to any 16c Ryzen. It is drawing 135w through the cores at full load. 7nm gives 50% power saving at the same performance, so ~68w for a 16c at TR clocks. Add the IF power, which is assumed to have remained at 45w, and we have 113w...well within what we could expect for a 16c Ryzen given that the 2700x went above its TDP.
There's nothing implausible with a 16c Ryzen hitting sensible TDP.

 

[Spartak]

Is it this?

Threadripper has it at a pretty constant 45W from 16-32 threads, which would explain the high idling of the ES that AdoredTV caught at the start of the demo.

The estimated TDP for the ES core would be around 40W then. So around 10% lower clocks for the 16core could fit within that 105W TDP, with XFR pushing it another 15-20W.

 

[PotatoWithEarsOnSide]

I should add; that TR is on a less efficient GF 14nm process too.

 

[Paratus]

Did anyone bother to check the area of the rome IO die?

View attachment 2386

It's exactly the same width as two zen2 chiplets and three rows in length or 6x the area of a chiplet.
If you divide that in 4 you get 1,5x the area of the chiplet, which is EXACTLY the die size of the ryzen3000 IO (122 = 1.5*81mm2)

Boy AdoreTV sure seems to be on to something with their multiple chiplet / quarter IO die rumors.

 

[Kenmitch]

Would it be possible to create a Ryzen 3000 cpu consisting of 1 I/O die + 1 zen2 chiplet + 1 L4 cache chiplet? A bit like the 5775C but without the iGPU. Maybe this would alleviate poor memory latency.

It's only limited by AMD's imagination. That and the unknown design limitations. Cache, gpu, more cores, small cores, high speed flash storage for OS....Will be interesting too see how it pans out.

 

[dlerious]

It's a igpu cpu with disabled, probably faulty igpu. They have cpu shortages and by selling chips with non-functioning igpu they can sell more units.

Only sane thing to AMD do is just the same, desktop IO will have also GPU and they could sell chips with GPU enabled or disabled. There's no point of doing IO-chip for desktop without iGPU - only reason to have one is that they can reuse non-perfect Rome chips.

I get why Intel would want to sell chips with disabled faulty iGPUs. What I don't get is why they would do it if it's nothing more than an enthusiast niche that OEMs will only sell high end game systems for, especially considering the 9350KF isn't exactly a high end chip.

I was replying specifically to this quote:
"Without iGPU desktop ryzen will remain an enthusiast niche....no OEM will touch it beyond high end/game systems "