The "problem" with the ES running @ 3.9-4Ghz is the 15%+ increase in IPC over Zen+ in order to get the 2050 CB score. AMD mentioned changes in Zen 2 that are bound to increase IPC by increasing efficiency, which has the "unfortunate" side-effect of decreasing SMT yields, which in turn means that single-threaded IPC increase for CB15 would need to be even higher, say something like 20% to throw a number around.

Did anyone bother to check the area of the rome IO die?

View attachment 2386

It's exactly the same width as two zen2 chiplets and three rows in length or 6x the area of a chiplet.

If you divide that in 4 you get 1,5x the area of the chiplet, which is EXACTLY the die size of the ryzen3000 IO (122 = 1.5*81mm2)

View attachment 2386

It's exactly the same width as two zen2 chiplets and three rows in length or 6x the area of a chiplet.

If you divide that in 4 you get 1,5x the area of the chiplet, which is EXACTLY the die size of the ryzen3000 IO (122 = 1.5*81mm2)

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