Speculation: Ryzen 3000 series

[exquisitechar]

The "problem" with the ES running @ 3.9-4Ghz is the 15%+ increase in IPC over Zen+ in order to get the 2050 CB score. AMD mentioned changes in Zen 2 that are bound to increase IPC by increasing efficiency, which has the "unfortunate" side-effect of decreasing SMT yields, which in turn means that single-threaded IPC increase for CB15 would need to be even higher, say something like 20% to throw a number around.

Don't be so sure of that. Zen 2 could have even higher SMT yields if they implemented some ideas that didn't make it into Zen, we don't know enough to say anything conclusive for now.

Did anyone bother to check the area of the rome IO die?

View attachment 2386

It's exactly the same width as two zen2 chiplets and three rows in length or 6x the area of a chiplet.
If you divide that in 4 you get 1,5x the area of the chiplet, which is EXACTLY the die size of the ryzen3000 IO (122 = 1.5*81mm2)

Yeah, I'm pretty sure people have already done measurements, IIRC the Ryzen IO die pretty much is around a quarter of Rome's, which, as you say, can be seen even by looking at them. Just like for Rome, forget about L4 cache...though I was hopeful for an iGPU as well.

 

[exquisitechar]

Oh, here are @kokhua 's measurements.

 

[Spartak]

There is plenty of die space left above and underneath the IO die, and I can't imagine these dies being so expensive to fab at GF.

Without iGPU desktop ryzen will remain an enthusiast niche....no OEM will touch it beyond high end/game systems.

 

[Spartak]

Oh, here are @kokhua 's measurements.

looking more closely to the anandtech estimate, the IOdie has much more shadow around compared to the chiplet. Seems they underestimated the IO and overestimated zen2 area.

Still, the 16mm2 difference (131-1.5*77) doesnt sound enough for even a tiny iGPU to be included.

 

[DrMrLordX]

Without iGPU desktop ryzen will remain an enthusiast niche....no OEM will touch it beyond high end/game systems.

Eh? HP Envy line features R3-1200 and R5-1400 options with RX 550 or 580 dGPU.

 

[exquisitechar]

not sure if these are more reliable then those from anandtech since it isnt superimposed on the original die shot. Even then, the difference wouldnt allow even a tiny iGPU.

Yeah, I'm not sure either, but it isn't a big difference.

 

[PotatoWithEarsOnSide]

It's pretty close though, isn't it?

Not so sure about this, but maybe AMD put what would be needed to support Threadripper (eg: quad channel memory and the extra PCIe lanes) on the IO die and both Ryzen and Threadripper share the same IO die.

That implies quad-channel Ryzen. If that were the case, we'd know about it for sure.

 

[dlerious]

There is plenty of die space left above and underneath the IO die, and I can't imagine these dies being so expensive to fab at GF.

Without iGPU desktop ryzen will remain an enthusiast niche....no OEM will touch it beyond high end/game systems.

I have to wonder why Intel would introduced the F processors like the 4-core 4 thread i3-9350KF then. That doesn't seem like a high-end CPU.

 

[moinmoin]

Is it? For me it sure looks just about one quarter of Rome IO-die.

Rome IO-die is massive, AMD will have to manufacture many of them to get enough fully working ones. If they can split IO-die to smaller ones it makes desktop-IO chip practically free.

AMD did show Rome IO die layout, it's configured so that every quarter of it will have 2*memory channel, 2 if links and quarter of io. It's also explains little bit odd chiplet arrangement of Rome.

The whole rumor started out with the desktop IOC just being a straight quarter cut of the server IOC just like you are writing there again.

Then came Ian Cutress' AT article where he writes:
"The IO-die is not exactly one quarter of the EPYC IO-die, as I predicted might be the case back the Rome server processor announcement launch, but it is actually somewhere between one quarter and one half."
Which both confirms the desktop IOC can't be a straight quarter cut of the server IOC like rumored, and supports AMD's keynote statement that it's specific for the desktop.

But why is it bigger than a quarter, not smaller considering on Zeppelin desktop used far less of the uncore than server? That's the question right now. Whether it's L4$, some tiny iGPU or something else we'll have to see.

 

[exquisitechar]

The whole rumor started out with the desktop IOC just being a straight quarter cut of the server IOC just like you are writing there again.

Then came Ian Cutress' AT article where he writes:
"The IO-die is not exactly one quarter of the EPYC IO-die, as I predicted might be the case back the Rome server processor announcement launch, but it is actually somewhere between one quarter and one half."
Which both confirms the desktop IOC can't be a straight quarter cut of the server IOC like rumored, and supports AMD's keynote statement that it's specific for the desktop.

But why is it bigger than a quarter, not smaller considering on Zeppelin desktop used far less of the uncore than server? That's the question right now. Whether it's L4$, some tiny iGPU or something else we'll have to see.

You're right, checking over it again, it is bigger than a quarter, which is peculiar given that it's for desktop. I still think there's no L4$.

 

[naukkis]

I have to wonder why Intel would introduced the F processors like the 4-core 4 thread i3-9350KF then. That doesn't seem like a high-end CPU.

It's a igpu cpu with disabled, probably faulty igpu. They have cpu shortages and by selling chips with non-functioning igpu they can sell more units.

Only sane thing to AMD do is just the same, desktop IO will have also GPU and they could sell chips with GPU enabled or disabled. There's no point of doing IO-chip for desktop without iGPU - only reason to have one is that they can reuse non-perfect Rome chips.

 

[Zapetu]

Oh, here are @kokhua 's measurements.

I have been very busy lately and it's nice that chiakokhua beat me to it with his illustrations. At some point I will also have mine out.

https://twitter.com/x/status/1084062218193317888

Still, the 16mm2 difference (131-1.5*77) doesnt sound enough for even a tiny iGPU to be included.

There might still be some server only logic in the Rome IO die that can be removed from the Matisse IO die, but sure, it would still be a very little space for an iGPU. Having some very basic iGPU (few Vega or even just few Polaris CUs) would be a nice addition for OEM office PCs / Ryzen Pro series, though. Whatever that extra space is for, it at least confirms that there's something extra there compared to Rome IO die.

Navi GPU chiplet would have been nice but clearly AMD is either saving something like it for later product lines or have different plans altogether. I was thinking earlier that a hypothetical Navi chiplet could have had just enough CUs and a large additional cache to compensate and balance for it being memory bandwidth starved with 2xDDR4. But it doesn't matter now since the current AM4 IO die and organic package (Matisse) isn't designed for a GPU chiplet in mind. Picasso is AMD's most recent APU for now and Matisse can almost certainly support one or two CPU chiplets. Is there a small iGPU for Ryzen Pro in Matisse IO die, we'll just have to wait and see.

In any case, Matisse is a really big change of mindset for AMD in terms of flexibility, reusability, efficient silicon use, binning for higher clock speeds (for higher end SKUs) and many other aspects. Who knew that something like WSA (Wafer Supply Agreement w/ GF) would seem to be part of the reason for such innovation and thinking outside the box. Sure, it may not be the only or even the biggest reason but it's something that AMD has to take into consideration, for now at least.

 

[Joe Braga]

I have been very busy lately and it's nice that chiakokhua beat me to it with his illustrations. At some point I will also have mine out.

https://twitter.com/x/status/1084062218193317888

There might still be some server only logic in the Rome IO die that can be removed from the Matisse IO die, but sure, it would still be a very little space for an iGPU. Having some very basic iGPU (few Vega or even just few Polaris CUs) would be a nice addition for OEM office PCs / Ryzen Pro series, though. Whatever that extra space is for, it at least confirms that there's something extra there compared to Rome IO die.

Navi GPU chiplet would have been nice but clearly AMD is either saving something like it for later product lines or have different plans altogether. I was thinking earlier that a hypothetical Navi chiplet could have had just enough CUs and a large additional cache to compensate and balance for it being memory bandwidth starved with 2xDDR4. But it doesn't matter now since the current AM4 IO die and organic package (Matisse) isn't designed for a GPU chiplet in mind. Picasso is AMD's most recent APU for now and Matisse can almost certainly support one or two CPU chiplets. Is there a small iGPU for Ryzen Pro in Matisse IO die, we'll just have to wait and see.

In any case, Matisse is a really big change of mindset for AMD in terms of flexibility, reusability, efficient silicon use, binning for higher clock speeds and many other aspects. Who knew that something like WSA (Wafer Supply Agreement w/ GF) would seem to be part of the reason for such innovation and thinking outside the box. Sure, it may not be the only or even the biggest reason but it's something that AMD has to take into consideration, for now at least.

Is it totally impossible to exist at least 1 Zen2 APU SKU and Ryzen Pro 3000 series SKUs with GPU?

 

[Zapetu]

Only sane thing to AMD do is just the same, desktop IO will have also GPU and they could sell chips with GPU enabled or disabled.

For Matisse that seems to be the case. Either there is a small iGPU on the IO die or there's some other reason why the IO die is the size it is.

Is it totally impossible to exist at least 1 Zen2 APU SKU and Ryzen Pro 3000 series SKUs with GPU?

Well, it depends on whatever that IO die has a small iGPU or not. AMD wanted to cut some rumors about GPU chiplet for the near future. So Matisse (2019 7nm desktop CPU line) is not going to have a GPU chiplet as an option. AMD's most recent APU, for at least most of if not all of this year, is going to be Picasso (12nm). Renoir is their next APU and while we're speculating, as a mobile design, it would be a monolithic design, it migh be based on chiplets also. It's way too early to speculate too much on that since it's likely a 2020 product.

 

[Jan Olšan]

GPU on separate chiplet makes no sense - it needs to be on the I/O chipset, because close coupling with the memory controller for maximum bandwidth is crucial.
However, there is not enough space on the I/O die for even a basic 2-3 CU iGPU. Based on the size, I expect only the same northbridge/southbridge connectivity that Zeppelin had to be there (it's the same 14nm node), only upgraded to PCIe 4.0 and perhaps with more evolved memory controller.

There probably just isn't any space left for fancy stuff, neither GPU nor extra cache. They would have to massively squish all the non-CCX blocks that Zeppelin had, or eliminate a lot of them.

 

[Spartak]

Interesting how they have stated Ryzen3 will have the same TDP range as Ryzen2.

How can they have 16-cores with a 14nm IO fit inside 105W TDP, unless the ES was already running at pretty high frequency? Rumors had the ES running at ~4.5GHz, so a 16-core running at ~4GHz all core *might* fit that TDP.

Together with there not being any G versions the AdoredTV leak is completely out of the window by now.

 

[Kenmitch]

Together with there not being any G versions the AdoredTV leak is completely out of the window now.

If you expected AMD to reveal all forms of pain heading Intels way this early I don't know what to say.

Time will prove him right or wrong....We just have to wait and see.

 

[Spartak]

That's not what i said or what most were expecting. I've always maintainted we'd see a mid '19 launch at the soonest.

I'm just saying that no products being announced at CES (just a demo), together with no G-versions or extended TDP versions into 125W-135W, the only thing correct on that list will likely be 16-core versions, which isnt that hard to guess when the core count is being doubled and you have half the power for the same performance.

My point was his leaks have already been disproven on three critical points.

 

[Joe Braga]

For Matisse that seems to be the case. Either there is a small iGPU on the IO die or there's some other reason why the IO die is the size it is.



Well, it depends on whatever that IO die has a small iGPU or not. AMD wanted to cut some rumors about GPU chiplet for the near future. So Matisse (2019 7nm desktop CPU line) is not going to have a GPU chiplet as an option. AMD's most recent APU, for at least most of if not all of this year, is going to be Picasso (12nm). Renoir is their next APU and while we're speculating, as a mobile design, it would be a monolithic design, it migh be based on chiplets also. It's way too early to speculate too much on that since it's likely a 2020 product.

But will it be based on 12nm+? Could it come with Vega+ CUs of GPUs?

 

[Joe Braga]

If you expected AMD to reveal all forms of pain heading Intels way this early I don't know what to say.

Time will prove him right or wrong....We just have to wait and see.

But Intel will launch GEN11 graphics for iGPUs that will go to substitute for UHD630?

 

[DarthKyrie]

If we work with previous ES speeds only, then why not be even more bound and consider a 3.6-3.7Ghz sample. That's what... just a 26% IPC jump over Zen+ in a SMT friendly workload. When was the last time Intel achieved a generational jump of 20% in IPC after Haswell?

I also have to wonder, what are the chances that the ES speed AMD would normally work with at this stage happens to match 9900K performance in CB15?

You need to remember that Zen 2 was supposed to be taking on Intel's 10nm chips.

 

[William Gaatjes]

There is plenty of die space left above and underneath the IO die, and I can't imagine these dies being so expensive to fab at GF.

Without iGPU desktop ryzen will remain an enthusiast niche....no OEM will touch it beyond high end/game systems.

It would make sense to have an igpu into the io die. Close to the memory controller is good for graphics performance and the chiplet can borrow heavily on the cache it has of it own to offload memory access. Also, i would not be surprised if AMD would go for a 12nm io/mem/igpu die + harvested zen2 chiplet with 6C/12T(but wih full cache, just as the 2600) for an affordable APU solution.

 

[Abwx]

Rumors had the ES running at ~4.5GHz

A Pinnacle Ridge would score about 2000 at 4.5GHz, so those rumours are stating that IPC improvement in CB is 2.85%, that s genuine rumours, indeed...

 

[PotatoWithEarsOnSide]

Interesting how they have stated Ryzen3 will have the same TDP range as Ryzen2.

How can they have 16-cores with a 14nm IO fit inside 105W TDP, unless the ES was already running at pretty high frequency? Rumors had the ES running at ~4.5GHz, so a 16-core running at ~4GHz all core *might* fit that TDP.

Together with there not being any G versions the AdoredTV leak is completely out of the window by now.

Can you expand upon this please?
What is it about the demo itself that tells you that they were running high frequencies, and that this necessitates lower clocks on a 16c SKU?
I'm seeing an ES sample that would have been running high voltages for stability, and not necessarily high clocks. In fact, anything 4.5GHz+ would represent IPC regression, which is highly unlikely.
Beyond that, we know that IF consumes huge chunks of power, and if we model that to the actual power usage for the demo, we can see that the 8c chiplet is likely not consuming much power at all. In fact, another 8c chiplet is unlikely to add more than 20-30w at the same frequency as in the demo. The 16c SKUs are supposedly 125w and 135w.
I'm fairly confident that AMD were sandbagging. Perhaps not by a massive amount, but by enough to get the message across.

 

[Hazy24]

Would it be possible to create a Ryzen 3000 cpu consisting of 1 I/O die + 1 zen2 chiplet + 1 L4 cache chiplet? A bit like the 5775C but without the iGPU. Maybe this would alleviate poor memory latency.