Speculation: Ryzen 3000 series

[NostaSeronx]

I went through they haystack of "Hyper-scheduling," "Hyper scheduling," and "hyperscheduling."

It lead me to this; https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/5d86p227x
(The dynamic simultaneous multithreaded processor)
Don't ask me how.

It isn't like Intel's Anaphase as DSMT is single SMT core focused. It might however use similar steps as it;
https://www.semanticscholar.org/pap...ópez/19bc8c04c1bdc1d49fd59b726b07c1d0a5c8aa91
https://www.researchgate.net/public...osition_Scheme_for_Speculative_Multithreading

Edit: 24-thread mode might be; 8 reverse-speculative threads, 8 non-speculative threads, 8 forward-speculative threads.

 

[DarthKyrie]

I went through they haystack of "Hyper-scheduling," "Hyper scheduling," and "hyperscheduling."

It lead me to this; https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/5d86p227x
(The dynamic simultaneous multithreaded processor)
Don't ask me how.

It isn't like Intel's Anaphase as DSMT is single core focused. It might however use similar steps as it;
https://www.semanticscholar.org/paper/Anaphase:-A-Fine-Grain-Thread-Decomposition-Scheme-Madriles-López/19bc8c04c1bdc1d49fd59b726b07c1d0a5c8aa91
https://www.researchgate.net/public...osition_Scheme_for_Speculative_Multithreading

Doesn't IBM use something like hyper-scheduling? I'm not familiar with how IBM sets things up.

 

[darkswordsman17]

https://www.reddit.com/r/Amd/comments/al5nou

We had ^^ leak 2 months ago. Hyper scheduler with specific modes enabled on 8 core chip (in a console dev kit- supposedly). Interestingly it shows 24 thread mode with Hyper Scheduler enabled.

That seems fake to me, I think mostly because of the GPU part, like an attempt at fanboy one-upmanship, "oh the PS5 will have Navi? Well the Xbox will get Arcturus." Also, 1GB of L4? eDRAM maybe?

If this CPU is getting launched in a couple of months, surely we be expecting some pretty constant leaks from this point on? Must be quite a few of them in the wild at this point.

It seems that either things are farther off or AMD has kept things locked up tightly. I almost wonder if the alleged motherboard issues might not be intentional (to keep leaks from mobo makers from happening). If AMD is doing their own chipset now, they're probably doing a lot of the testing and stuff in house. And they could test compatibility with previous by using boards that are already out themselves.

Perhaps there's something extra up AMD's sleeve and why they're being extra secretive. Seems that most people expect that empty place on the CPU package to be for a 2nd CPU die, but maybe its something else, like cache/eDRAM (that might make this hyperscheduling work where it'll keep a page of 24 threads and swap them in and out as it can, while being a big fast cache that would help with memory issues that might come from say, using an I/O chip; AMD knew people would speculate about it being for CPU or GPU die so it'd be a great misdirection).

Doesn't IBM use something like hyper-scheduling? I'm not familiar with how IBM sets things up.

Seeing that its about more threads, that was my first guess too. Doesn't IBM have some chips that have like 8 threads per core?

 

[amd6502]

We had ^^ leak 2 months ago. Hyper scheduler with specific modes enabled on 8 core chip (in a console dev kit- supposedly). Interestingly it shows 24 thread mode with Hyper Scheduler enabled.

Yes, the 24t is very interesting and nifty. I think what it might be is 16 big (SMT2) and 8 small/background threads. Each core, in addition to SMT, might be able to do coarse grain MT by quickly being able to retrieve the state of a sleeping thread from the L1.

A background thread might come active when there is a miss in the L3 (stated as 32MB), or maybe when L4 misses (1GB, see DownTheSky comment).

16t mode under non-SMT might be 8 big threads along with 8 small threads.

As people are saying, reverse SMT might be the ultimate feature of this scheduler, but looking at the enabled present features "SCHEDULER_FUSE1 (2 Threads)" is unchecked, and only "SCHEDULER_FUSE0 (1 Thread)" is shown as available. But maybe these are commas and not checkmarks for available modes.

Another take is that SCHEDULER_FUSE0 means that CCX0 is running 1 thread in rev-SMT (while CCX1 is doing standard SMT); and, that "SCHEDULER_FUSE1 (2 Threads)" means both CCX's are doing rev-SMT, the APU acting as essentially one monster dual core processor.

The interpretation of this summary screen is definitely hard to figure out. If it is a fake they sure are fooling me; it looks very plausible. It should be an interesting summer; I can't wait till this mystery is unveiled.

 

[amd6502]

Edit: 24-thread mode might be; 8 reverse-speculative threads, 8 non-speculative threads, 8 forward-speculative threads.

I kind of disagree on 24t mode being such a decomposition, but it would make sense to use the large number of cores for multiple speculative branches in the fuse modes.

My favorite interpretation now is that FUSE0 (1 Thread) refers to using the whole CCX0 (4 cores) in a full all out reverse SMT mode using all the tricks possible to get the highest performance. And the mode FUSE1 (2 Threads) using both CCX0 and CCX1 in this way.

 

[DrMrLordX]

Doesn't IBM have some chips that have like 8 threads per core?

Yes. POWER9 has 4-way and 8-way SMT variants.

 

[Topweasel]

Better to go with single or dual chiplet Epyc products.

Theatripper is another option. (do they have a lower cTDP setting??)

I really think quad salvage will exist just because of the sheer number of chiplets in production (my guess actually, in both 2+2 balanced and single ccx 4+0 configurations). Tiny * massively huge is still a pretty big number.

My guess is these will mostly be used for Ryzen 5 4c/8t. (The very few quad chiplets that don't cut the frequencies will be rare and saved for niche Epyc GPU compute APUs for release 2020 or after.)

Here is a hypothetical (rough guess) desktop portion of the product line:

3200g 3.6-3.9 4c/4t 8CU ryzen 3
3300g 3.4-3.8 4c/8t 8CU ryzen 3
3400g 3.8-4.1 4c/8t 11CU ryzen 5
3500 4.0-4.3 4c/8t 7nm ryzen 5
3500x 4.2-4.5 4c/8t 7nm ryzen 5
3565 3.5-4.0 6c/12t 0CU ryzen 5
3585 3.0-4.0 8c/16t 0CU ryzen 7
3600 4.0-4.5 6c/12t 7nm ryzen 7
3700 4.3-4.7 6c/12t 7nm ryzen 7
3800 4.1-4.7 8c/16t 7nm ryzen 7
3800x 4.4-4.8 8c/16t 7nm ryzen 7
3920x 4.2-4.8 12c/24t 7nm ryzen 9 (paper launch)

(7nm probably will also come with zero graphics CU, but nothing has been ruled out at this point).

Sorry I wanted to repond to this but I don't really have the energy for this. But There won't be single or dual chiplet Epyc's, I doubt they will do that with Threadripper either. They had to do diagonal chips to keep the chips heat sources manageable. That was with chips nearly 3 times the size. They picked the arrangement because it gave them 2 easy to manage configurations 4 and 8. You can save this for later and i'll eat crow. But I would super surprised if AMD releases either in any other configuration.

I will also rule out any APU functionality in any 7mm 3K Ryzen. It's unnecessary and people don't know what it would cost AMD to include it for all of us. AMD made many compromises to make RR on AM4 a thing and I am not sold that those would apply to these bigger chips. Also in a world where AMD is using to Matisse to catch up and possible take it to Intels high performance consumer chips they aren't going to want any intrusion of GPU power budgeting in getting the clocks up. For the people talking about dGPU's limiting business options, its mostly hogwash. If the TCO is cheaper with AMD or offers great performance for the dollar businesses don't care if there is a dGPU. This is more of an i3 market discussion and AMD already has APU's for that.

They will be able to salvage tons of chips. Will it be enough to keep up with the volume of CPU's AMD will need to ship that will use them probably. My discussion about salvaging had more to do with some kind of binning based on certain cores clocking higher than most on a chip and somehow still coming in below a cherry fully enabled chip and being used in the given configuration (like in a 2+2 environment I don't believe AMD can just use the two highest clockers on each CCX).

Also you have a lot of weird configurations. While it's possible AMD might save some weird bins for "custom" sku's for OEM's and ODMs. I doubt AMD will have that many cpu's in retail for that mid section. It drags down ASP, there isn't enough pricing devation, and just seems like a mess. I think there will be 3 4 cores, 2 with SMT, one of them being an X. 2 6c, 1 being an x, maybe 3 8c with one and X and one an X with a single 8c die (the 9900k killer imho). 2 12s (1 being an x) and 2 16c (one being an x). With the 12+c's going from $300-$600. There is no reason to sit on a 16c CPU unless the yields are low.

 

[Topweasel]

If this CPU is getting launched in a couple of months, surely we be expecting some pretty constant leaks from this point on? Must be quite a few of them in the wild at this point.

That's what we said with just about everything before, but honestly even going back as far BD, information has always seemed sparse until max about a week or 2 before release. I think it's based on sheer numbers. Not as many people have the chips that are willing to put there jobs at risk. So we have to wait till the review samples and people to break NDA which happens more often. Intel just sends out so many more chips for development testing so in a numbers game you have a much higher chance of someone pushing the limits of what they can do with their engineering sample.

 

[amd6502]

Sorry I wanted to repond to this but I don't really have the energy for this. But There won't be single or dual chiplet Epyc's, I doubt they will do that with Threadripper either. They had to do diagonal chips to keep the chips heat sources manageable. That was with chips nearly 3 times the size. They picked the arrangement because it gave them 2 easy to manage configurations 4 and 8. You can save this for later and i'll eat crow. But I would super surprised if AMD releases either in any other configuration.

Yes you're correct, the standard (LGA) Epyc do appear to be all quad dies, while the embedded (BGA?) appear to be single die for dual channel models and a pair of dies for the quad channel models. https://en.wikipedia.org/wiki/Epyc The 8GB of L3 per CCX lets one get a pretty good guess at the number of active dies. Accoring to wikichip, some (most?/all?) Epyc are B2 stepping, so more closely related to Pinnacles than to Summit.

I will also rule out any APU functionality in any 7mm 3K Ryzen. It's unnecessary and people don't know what it would cost AMD to include it for all of us. AMD made many compromises to make RR on AM4 a thing and I am not sold that those would apply to these bigger chips. Also in a world where AMD is using to Matisse to catch up and possible take it to Intels high performance consumer chips they aren't going to want any intrusion of GPU power budgeting in getting the clocks up. For the people talking about dGPU's limiting business options, its mostly hogwash. If the TCO is cheaper with AMD or offers great performance for the dollar businesses don't care if there is a dGPU. This is more of an i3 market discussion and AMD already has APU's for that.
[...]
Also you have a lot of weird configurations. While it's possible AMD might save some weird bins for "custom" sku's for OEM's and ODMs. I doubt AMD will have that many cpu's in retail for that mid section. It

I wonder if these OEM bins will not work on some consumer AM4 boards. I've heard rumor they are running out of ROM storage capacity for the growing number of AM4 models. I wonder what the deal is with all the PRO models; are they just mostly aliases with maybe just the minor difference in whether the coprocessor is active for remote management ability?

As for basic GPU, I don't know how it works for AM4, but I've built plenty of FM2+ systems, and some of them with Athlon X4. I think it's just awkward that there are dead video-out ports (from the mobo). Your basic office worker could get easily confused and think the video or monitor is busted; unless that issue is addressed in AM4 (or capped off by OEM) it's just not idiot proof enough, or too awkward, for business builds. No onboard video also rules out some ultra slim SFF form factors, or requires half height cards on the remaining SFF cases. That said a 2400g is more than enough for 90% of business PCs. Not having iGPU, I think they could easily loose some upper end business sales: super high performance workstations and laptops that need minimal GPU. Sadly, going by the hub die size, it does look like basic iGPU seems unlikely.

I suppose another solution around the video problem could be to have BGA ITX motherboards with onboard video to address the business market, along with a sibling laptop board. That would bring 16 threads to both mobile and workstation.

 

[Topweasel]

As for basic GPU, I don't know how it works for AM4, but I've built plenty of FM2+ systems, and some of them with Athlon X4. I think it's just awkward that there are dead video-out ports (from the mobo). Your basic office worker could get easily confused and think the video or monitor is busted; unless that issue is addressed in AM4 (or capped off by OEM) it's just not idiot proof enough, or too awkward, for business builds. No onboard video also rules out some ultra slim SFF form factors, or requires half height cards on the remaining SFF cases. That said a 2400g is more than enough for 90% of business PCs. Not having iGPU, I think they could easily loose some upper end business sales: super high performance workstations and laptops that need minimal GPU. Sadly, going by the hub die size, it does look like basic iGPU seems unlikely.

I suppose another solution around the video problem could be to have BGA ITX motherboards with onboard video to address the business market, along with a sibling laptop board. That would bring 16 threads to both mobile and workstation.

The bolded part is an imaginary market that doesn't actually exist. Heck look at Dell Precision and their non-Ultrabook latitudes. Independent of users needs I can't order those without these cheap crappy dGPU's. That's because the market is so small Dell doesn't want to make a cooler just for the I7 models without a dGPU. Performance or even business laptops adding a $30 with the option to upgrade covers the ground they need. It allows OEMs to use RR to cover the cheap end where $30 is significant and at the higher can offer enough value to make that $30 a wash all on the same platform and parts supply. Heck that's the only reason AMD worked with OEM's into making a single socket rather than 2 like they had in the past.

 

[Yotsugi]

Seeing that its about more threads, that was my first guess too. Doesn't IBM have some chips that have like 8 threads per core?

Knights Landing was also SMT4.

 

[Veradun]

The bolded part is an imaginary market that doesn't actually exist. Heck look at Dell Precision and their non-Ultrabook latitudes. Independent of users needs I can't order those without these cheap crappy dGPU's. That's because the market is so small Dell doesn't want to make a cooler just for the I7 models without a dGPU. Performance or even business laptops adding a $30 with the option to upgrade covers the ground they need. It allows OEMs to use RR to cover the cheap end where $30 is significant and at the higher can offer enough value to make that $30 a wash all on the same platform and parts supply. Heck that's the only reason AMD worked with OEM's into making a single socket rather than 2 like they had in the past.

I work in a 3000 employees reality where every single employee has been given a DELL machine with an Intel CPU and a Radeon

I agree that market doesn't exist

 

[Fanatical Meat]

More motherboard forum thing but I feel the context fits this thread.

Biostar will release its next gen AMD motherboard during Computex
All signs point to it being an X570 board

https://www.google.com/amp/s/amp.to...md-x570-motherboards-computex-2019,39175.html

 

[IEC]

More motherboard forum thing but I feel the context fits this thread.

Biostar will release its next gen AMD motherboard during Computex
All signs point to it being an X570 board

https://www.google.com/amp/s/amp.to...md-x570-motherboards-computex-2019,39175.html

I spy triple m.2 and a fan on the chipset heatsink... those VRM sinks look pretty beefy as well. I guess it will definitely support a AM4 CPU with "More than 8 cores"

 

[Fanatical Meat]

I spy triple m.2 and a fan on the chipset heatsink... those VRM sinks look pretty beefy as well. I guess it will definitely support a AM4 CPU with "More than 8 cores"

There’s this from ASRock but it could be a 50th anniversary thing

https://www.reddit.com/r/Amd/comments/bh5aje

 

[krumme]

As a percentage? As market penetration increase, they might be reserved for Pro models assigned to business PCs. For the retail market, a 6C could be the real base model. Also, we don't know for sure, if the same limitations exist to utilizing cores in the chiplet.

I tend to agree it will be stupid to go lower than 6c and erode your brand for the new 3000 series. 4c can be reserved for pro later or some China only product

When you have a potent and efficient core it's time to push the moar core narrative. Not when you have a slow inefficient cpu like bd. It's an important distinction for brand development. We saw with bd how awful wrong it can go. But you need the right product for it. The 3000 might be such a product. Amd is not exactly masters of this game so let's wait and see. But if they have the opportunity I hope they see how relatively cheap they can build brand value by just allocating a few cpu to lower marginal revenue.

 

[amd6502]

I tend to agree it will be stupid to go lower than 6c and erode your brand for the new 3000 series. 4c can be reserved for pro later or some China only product

Unlikely I think. Yields are worse than 14nm Summit which had quite a few quad salvage. Given this, there's no reason they would stop salvaging quads now. The normal pattern is release 8c and 6c, accumulate salvage dies for three to 4 months, then release these somewhat rare salvages (quite rare, relative to 6c salvage); meaning we expect 4c/8t 7nm Ryzen 5.

A big part of mainstream is those for whom Ryzen 7 is a bit too pricey and overkill, like budget gamers just wanting higher sparse thread. They will gladly take (at about the same price point ~$150) a higher clocking 7nm 4c/8t over a 3400g, even if it means no iGPU.

These things are very capable; even the modestly clocked 2400g has 8 pretty strong threads that just about always outperform an FX-8300. So not a multithread slouch by any means.

Now a 7nm 6c/12 should exceed a 1700 in all ways, and be close or exceed a 2700, so imho it's going to be a Ryzen 7 part, upwards of $220.

 

[Hans Gruber]

Unlikely I think. Yields are worse than 14nm Summit which had quite a few quad salvage. Given this, there's no reason they would stop salvaging quads now. The normal pattern is release 8c and 6c, accumulate salvage dies for three to 4 months, then release these somewhat rare salvages (quite rare, relative to 6c salvage); meaning we expect 4c/8t 7nm Ryzen 5.

A big part of mainstream is those for whom Ryzen 7 is a bit too pricey and overkill, like budget gamers just wanting higher sparse thread. They will gladly take (at about the same price point ~$150) a higher clocking 7nm 4c/8t over a 3400g, even if it means no iGPU.

These things are very capable; even the modestly clocked 2400g has 8 pretty strong threads that just about always outperform an FX-8300. So not a multithread slouch by any means.

Now a 7nm 6c/12 should exceed a 1700 in all ways, and be close or exceed a 2700, so imho it's going to be a Ryzen 7 part, upwards of $220.

Please do not cite any AMD part prior to Ryzen. It has been so long since the glory days of AMD prior to Core2Duo. An FX-8300 is pure junk.

 

[Veradun]

Unlikely I think. Yields are worse than 14nm Summit which had quite a few quad salvage. Given this, there's no reason they would stop salvaging quads now.

Remember a lineup is not only made because of salvaging needs, but also for segmentation.

When Ryzen 1000 arrived they missed something to offer in the 4c segment, because dozer was not as performing as zen. In fact they had 4 different 4c SKUs under the 1000 branding.

Once Ryzen 2000 came they already had Ryzen 2000G to cover that segment, in fact they only had 2 4c nonG SKUs.

It's definitely possible they will offer 6c as a minimum for nonG SKUs this time, as 4c is well covered, and use the bad dies with only 4 working cores in EPYC SKUs that want all the lanes and memory channels but don't need a lot of cores (think storage nodes, for example).

 

[maddie]

Unlikely I think. Yields are worse than 14nm Summit which had quite a few quad salvage. Given this, there's no reason they would stop salvaging quads now. The normal pattern is release 8c and 6c, accumulate salvage dies for three to 4 months, then release these somewhat rare salvages (quite rare, relative to 6c salvage); meaning we expect 4c/8t 7nm Ryzen 5.

A big part of mainstream is those for whom Ryzen 7 is a bit too pricey and overkill, like budget gamers just wanting higher sparse thread. They will gladly take (at about the same price point ~$150) a higher clocking 7nm 4c/8t over a 3400g, even if it means no iGPU.

These things are very capable; even the modestly clocked 2400g has 8 pretty strong threads that just about always outperform an FX-8300. So not a multithread slouch by any means.

Now a 7nm 6c/12 should exceed a 1700 in all ways, and be close or exceed a 2700, so imho it's going to be a Ryzen 7 part, upwards of $220.

Yields by itself is not a useful indicator. Die size is critical. What is the chance of getting 4 defects on a 70mm^2 die to make only 4 cores usable? I think this would be a very very tiny percentage.

A 6C could be eminently suitable as the lowest offered retail model.

 

[jpiniero]

Unless they've changed this, one defective core means they have to either disable the entire CCX or a core in the other CCX (good or not). Two defective cores in the same CCX means you are only getting 4 cores out of the die.

 

[amd6502]

They can be, but with a yield of only ~75% or 80% true salvaging is significant. I also see zero advantages over throwing these dies into a landfill.

They can also raise that percentage up or down, depending on how aggressively they target the frequencies (and my guess is that they will target them aggressively). That means there will be plenty of 4C salvage to go around.

The timing is looking good, if they release before June 30 these quads should hit the streets Q4 and before Thanksgiving.

It's a good way to get rid of bottom of the barrel binning; these clock about half a GHz less than top binned dies (dies with high defect number usually have quite a few cores that clock poorly). And even such bottom binned parts will be able to slightly outclock the other 4c/8t in the same price range. So this is a guess of the bottom of the Ryzen 5 3000:

3400g 3.8-4.1 4c/8t 11CU ~$150
3500 4.0-4.3 4c/8t 7nm ~$145
3500x 4.2-4.5 4c/8t 7nm ~$160

So, roughly the same price, but you'd loose a very nice GPU but gain a few hundred MHz and double up your FPU.

 

[Yotsugi]

That means there will be plenty of 4C salvage to go around.

You won't ever see 4c CCDs in anything client.
Only in the very special, very pricey Rome SKUs for those with extra stingy per-C licensing.

 

[maddie]

They can be, but with a yield of only ~75% or 80% true salvaging is significant. I also see zero advantages over throwing these dies into a landfill.

They can also raise that percentage up or down, depending on how aggressively they target the frequencies (and my guess is that they will target them aggressively). That means there will be plenty of 4C salvage to go around.

How much is plenty?

If I use the 80% number, this means 20% with more than 1 defect and then is fairly accurate in saying, assuming a random distribution, that of those, a further 20% will have 2+ defects equaling 4% of total die. Of this 4% a bit less than 1/2 will have 1 defect in each CCX. It's the same concept as used for multiple HDD failure or multi engine safety.

I get 80% full 8C, 17+% capable of 6C die and the rest 4C or worse.

 

[amd6502]

How much is plenty?

If I use the 80% number, this means 20% with more than 1 defect and then is fairly accurate in saying, assuming a random distribution, that of those, a further 20% will have 2+ defects equaling 4% of total die. Of this 4% a bit less than 1/2 will have 1 defect in each CCX. It's the same concept as used for multiple HDD failure or multi engine safety.

I get 80% full 8C, 17+% capable of 6C die and the rest 4C or worse.

Any defect in the L3 will get binned as quadcore. I believe they doubled up the L3 (so the area is not trivial).

If there are two defects in a CCX it most likely will need to be salvaged as a quadcore.

If there is one defect in each CCX I would give it ballpark 3:2 chance it could get salvaged as 6c rather than 4c.

Still, you are more or less talking about something slightly upwards of 4%.

And the big issue is this is assuming they are willing to salvage for the maximum number of cores without any regard for the frequencies of the cores.

To do a realistic calculation you would need a probability distribution of the maximum frequency a core can perform at, at a desired stock max voltage (say 1.2v). You would assume it's gaussian probably and try to find the standard deviation, given some large number (>1000) samples. Once you have the avg and std deviation, given a target frequency, you could do a calculation for the the % of 6c and 4c dies.

Without those three numbers we can only make ballpark guesses. Mine is that the number of quad salvages are going to be in the high single digit (~7%).

With the uncore moved to the hub, I am thinking that Epyc Rome models might be anything from 1 chiplet to 8 chiplet. Rome is going to suck up a huge number of chiplets. Ryzen 3000 will add to that number. Rome gets first dibs on highest quality (8c) silicon, since reliability and quality are top importance, and clients pay the top $. I doubt you are going to have a lot of bottom of the barrel go to Rome, if any at all. So in my opinion it follows pretty naturally that these go to supplement the 3400g, given Zen2's unique advantages of being able to go higher than 4.1ghz and having a doubled up FPU.