Speculation: Ryzen 3000 series

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What will Ryzen 3000 for AM4 look like?


  • Total voters
    190

Topweasel

Diamond Member
Oct 19, 2000
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Agree with the high clocked 8C part. That was one I predict to be the highest clocking part, but (2) 4C chiplets binned for the highest clocked cores and with the greatest area of silicon to dissipate heat.

A 50th anniversary special edition?
I think you will find the clock potential being hire on single chiplet, CPU over a dual Chiplet. It should be less of an issue but on Zen 2 because of less of other stuff. But generally turning off cores out of die don't generating the savings people estimate. Finding a really good cherry single chiplet with full power allotment is going be a much better option.
 

maddie

Platinum Member
Jul 18, 2010
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I think you will find the clock potential being hire on single chiplet, CPU over a dual Chiplet. It should be less of an issue but on Zen 2 because of less of other stuff. But generally turning off cores out of die don't generating the savings people estimate. Finding a really good cherry single chiplet with full power allotment is going be a much better option.
What I meant was the always present variation between cores even in a premium binned chiplet.

In other words, take any chiplet, and the 8 cores within it will themselves have Gaussian distribution in clock potential, a bell curve distribution. Fuse off the 4 slower cores and that same chiplet will have a higher clock potential overall than the same chiplet using all 8 cores. Figuratively, you end up cutting off the left hand side of the bell curve.

Remember the AMD research paper showing how a composite CPU made up of chiplets could clock higher than a monolithic die as you could bin the chiplets and assemble CPUs made up of higher clocked bins which shifts the bell curve to the right an a way almost impossible with a monolithic layout. Figure 3 on page 2
http://www.eecg.toronto.edu/~enright/Kannan_MICRO48.pdf

Ignoring power :))), two of these will clock higher than a single chiplet from the same bin. This is what I mean as to a limited anniversary edition. Not a regular offering as it will be more expensive to fabricate, and basically discards operational cores. You might only get 5-10%, but this can a special CPU.
 

Topweasel

Diamond Member
Oct 19, 2000
4,768
363
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What I meant was the always present variation between cores even in a premium binned chiplet.

In other words, take any chiplet, and the 8 cores within it will themselves have Gaussian distribution in clock potential, a bell curve distribution. Fuse off the 4 slower cores and that same chiplet will have a higher clock potential overall than the same chiplet using all 8 cores. Figuratively, you end up cutting off the left hand side of the bell curve.

Remember the AMD research paper showing how a composite CPU made up of chiplets could clock higher than a monolithic die as you could bin the chiplets and assemble CPUs made up of higher clocked bins which shifts the bell curve to the right an a way almost impossible with a monolithic layout. Figure 3 on page 2
http://www.eecg.toronto.edu/~enright/Kannan_MICRO48.pdf

Ignoring power :))), two of these will clock higher than a single chiplet from the same bin. This is what I mean as to a limited anniversary edition. Not a regular offering as it will be more expensive to fabricate, and basically discards operational cores. You might only get 5-10%, but this can a special CPU.
3 Big keys.
1. That curve was based on 1 die with the same number of cores as the two die put together. It's meant more to compare a 16c vs a 2x8c. Chopping up two dies of the same type and glueing those two together.
2. To continue that point and it was one raised by Adored, is the idea that Intel can only have the 5GHz top K CPU's because of the shear volume of any particular die they make. How that feeds into what AMD is saying is that on top of the power requirements, on top of the lower yields a larger chip would present. Dual chiplets presents AMD twice as many dies to bin. You double the count of dies you double the amount of cherry chips to enough to offer a sku based on it's performance. You get enough volume of dies you slide that marker for volume a given clock speed over that much more. For company like AMD that is hurting in market penetration them artificially inflating volume by going the chipset route not only increases yields but increases potential clockspeed of their sku's by giving them more chips to bin.
3. There is a lot of assumption on AMD's process for fusing off dies. I doubt it's as cut and dry as this is a slow core, cut it up. They seem to have to options mirror ccx's and a disabled CCX. My guess is where they start disabling on the mirrored CCX's is the same on all chips (outside in) and the disabled CCX might even be as specific (Farthest from IO or second die interconnects). AMD can't take chance of having the CPU's performance being to different per clock based on the configuration of disabled cores and their location in regards to the rest of the cores.

In the end I doubt AMD can find and run enough cut down dies run in the same power envelope at a faster speed than they could with a single die configuration. Now if we were talking two bespoke 4 core dies instead of 2 of the exact same dies that 8c chiplet version would be, then you would probably be right.
 

Ajay

Diamond Member
Jan 8, 2001
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Dual chiplets presents AMD twice as many dies to bin. You double the count of dies you double the amount of cherry chips to enough to offer a sku based on it's performance. You get enough volume of dies you slide that marker for volume a given clock speed over that much more. For company like AMD that is hurting in market penetration them artificially inflating volume by going the chipset route not only increases yields but increases potential clockspeed of their sku's by giving them more chips to bin.
I don’t think so. AMD has, roughly, a fixed number of Zen2 chiplets for all its 7nm product (Matisse and Rome). Typically, servers CPUs get the best bins.
 

Tuna-Fish

Senior member
Mar 4, 2011
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I don’t think so. AMD has, roughly, a fixed number of Zen2 chiplets for all its 7nm product (Matisse and Rome). Typically, servers CPUs get the best bins.
Excluding low volume specialist CPUs, server chips prefer low power consumption to high clock speeds. Those are two different qualities, that are only somewhat correlated. Most of the very highest clocking chips are not particularly low power, and most of the least consuming chips do not clock particularly high.
 

jpiniero

Diamond Member
Oct 1, 2010
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Excluding low volume specialist CPUs
Those specialist CPUs will pay dearly for the A+ bins though, but only if AMD delivers on IPC and clocks. Either way I imagine they would want to save the rest of the A+ for Threadripper.
 

Topweasel

Diamond Member
Oct 19, 2000
4,768
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I don’t think so. AMD has, roughly, a fixed number of Zen2 chiplets for all its 7nm product (Matisse and Rome). Typically, servers CPUs get the best bins.
As noted the below the best clockers are often not the best dies to use in a server setup. I could AMD using some really good high clocked chips in a 4 chiplet 16-32c setup. Or maybe some ODM "custom" CPU's with a higher TDP if the companies really wanted it. But if the server demand even in your suggestion was going to limit AMD on their Ryzen offering, then we are talking about EPYC destroying the Ryzen market. I think it's probably going to be more reasonable as server and OEM markets take baby steps adopting AMD products. We don't know yeild rates, how much max allotment from TSMC is going to be and what general demand is going to be. What we do no is that even if AMD doesn't budge from where they are market wise they will have nearly 3x the chips from wafer and that is where on top of the process, the clock increases come from more samples, not hoping you can chop of the right cores from the right chiplets to each out a little more speed. It's pretty academic because even if AMD wanted to up the peak usage and TDP of a CPU. They will still have a cap in mind and in that situation a single chiplet CPU will always have the advantage.
 

Ajay

Diamond Member
Jan 8, 2001
5,071
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Excluding low volume specialist CPUs, server chips prefer low power consumption to high clock speeds. Those are two different qualities, that are only somewhat correlated. Most of the very highest clocking chips are not particularly low power, and most of the least consuming chips do not clock particularly high.
Well, in general, better xtor electrostatics (say like low leakage) will yield benefits in both low power and clock headroom. I suppose a cpu with good electrostatics could have a 'bad' metal layer with higher parasitic capacitance that would generate problems a higher clocks - in that regard, I would agree with your statement :)
 

Topweasel

Diamond Member
Oct 19, 2000
4,768
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Well, in general, better xtor electrostatics (say like low leakage) will yield benefits in both low power and clock headroom. I suppose a cpu with good electrostatics could have a 'bad' metal layer with higher parasitic capacitance that would generate problems a higher clocks - in that regard, I would agree with your statement :)
The problem is that for max clocks you generally have to bleed off extra power. If your die is really really good about not leaking as much power it tends to resist higher clocks. With low power leakage you tend to get better clocks in any given power level and therefore more headroom but the upper end potential is released. This means that by picking cherry picked dies for low leakage AMD could sell an all clock turbo 2.5GHz 64Epyc at 180w TDP, where the big grouping in the bell curve of chips would have to be limited to 2.2GHz in that same TDP. But it might mean any of those dies might max out at 4GHz instead of the 4.7GHz at max clock of a normal die (or 4.5GHz at a reasonable TDP) and so on. Tons of variables there though. But the end result is you do get a clock overhead, but not on potential, but based on power budget.
 
Oct 18, 2013
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The problem is that for max clocks you generally have to bleed off extra power. If your die is really really good about not leaking as much power it tends to resist higher clocks. With low power leakage you tend to get better clocks in any given power level and therefore more headroom but the upper end potential is released. This means that by picking cherry picked dies for low leakage AMD could sell an all clock turbo 2.5GHz 64Epyc at 180w TDP, where the big grouping in the bell curve of chips would have to be limited to 2.2GHz in that same TDP. But it might mean any of those dies might max out at 4GHz instead of the 4.7GHz at max clock of a normal die (or 4.5GHz at a reasonable TDP) and so on. Tons of variables there though. But the end result is you do get a clock overhead, but not on potential, but based on power budget.
Why would bleeding lead to higher clocks?
 

Topweasel

Diamond Member
Oct 19, 2000
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Why would bleeding lead to higher clocks?
Pressure. If some electrons can't make it out of the seal then they just act as more friction and slow down movement for the rest of the electrons as they try to go really fast. The better the die is in keeping the power in the harder is to get all of it to travel through fast enough. It's probably not scientifically the best answer and the simpler chips that leak more clock more is about the best answer you get. It might not even really be a friction speed issue and more of an errosion issue, keep to many electrons in the pipeline at those power levels (needed for the clock speed) and you do more damage to the CPU faster.

Edit: The more I think about it my head the more I lead to B.) Erossion. We already know on at least Zen that pushing beyond a certain point (1.4v?) leads to quick erosion. I am pretty sure that applies even lower to less leaky CPU's and why a Ryzen 1700 whos dies were probably picked for being on the less leaky side generally capped out a good couple hundred MHz below the 1700x and 1800x and why it seems guys with 1700's and 1600's overclocking with ~1.3v might be seeing long term erosion, at lower clocks, and lower power settings.
 
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NostaSeronx

Platinum Member
Sep 18, 2011
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Oct 18, 2013
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Pressure. If some electrons can't make it out of the seal then they just act as more friction and slow down movement for the rest of the electrons as they try to go really fast. The better the die is in keeping the power in the harder is to get all of it to travel through fast enough. It's probably not scientifically the best answer and the simpler chips that leak more clock more is about the best answer you get. It might not even really be a friction speed issue and more of an errosion issue, keep to many electrons in the pipeline at those power levels (needed for the clock speed) and you do more damage to the CPU faster.

Edit: The more I think about it my head the more I lead to B.) Erossion. We already know on at least Zen that pushing beyond a certain point (1.4v?) leads to quick erosion. I am pretty sure that applies even lower to less leaky CPU's and why a Ryzen 1700 whos dies were probably picked for being on the less leaky side generally capped out a good couple hundred MHz below the 1700x and 1800x and why it seems guys with 1700's and 1600's overclocking with ~1.3v might be seeing long term erosion, at lower clocks, and lower power settings.
Interesting. I started looking it up after your post, because it did not make sense with how I was conceptualizing it. But, it appears that the same forces that keep the electrons constrained also act as a type of friction so that the more you try to force through the higher the friction.
 

Ajay

Diamond Member
Jan 8, 2001
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Leaky chips tend to clock higher.
Hmm. Higher clocked chips tend to run at a higher vCore which causes an increase in dynamic power. IIRC, leakier xtors only allowed higher frequencies in planar, not in FinFETs.
 

Topweasel

Diamond Member
Oct 19, 2000
4,768
363
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They run at high vcore because with higher leakage it requires high vcore to maintain clocks. It's the catch 22 and why these chips are terrible for epyc. Not sure what you see is wrong with the math. Just because it requires a higher vcore at normal level clocks doesn't mean that it can't clock higher even if it requires even that much more power.
 
Apr 27, 2000
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Hmm. Higher clocked chips tend to run at a higher vCore which causes an increase in dynamic power. IIRC, leakier xtors only allowed higher frequencies in planar, not in FinFETs.
They run at high vcore because with higher leakage it requires high vcore to maintain clocks. It's the catch 22 and why these chips are terrible for epyc. Not sure what you see is wrong with the math. Just because it requires a higher vcore at normal level clocks doesn't mean that it can't clock higher even if it requires even that much more power.
Maybe I'm off-base with FinFET-based chips, but from my experience, leaky chips require more current and less voltage at any given clock. Usually the current/voltage curve versus clockspeed on a leaky vs non-leaky chip will put total power usage at any given clockspeed higher for the leaky chip.

If you compare R7 1700s vs. R7 1800x chips, it certainly looks like AMD binned for higher leakage on the 1800x since they can be power hogs, even when running the same clock as a 1700. 1800x chips were more likely to hit 4.0 GHz and higher, though. Silicon Lottery's figures reflected that fact.
 
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Kenmitch

Diamond Member
Oct 10, 1999
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Hans Gruber

Senior member
Dec 23, 2006
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Instead of speculating on the Zen 2 CPU's. Has anybody caught a benchmark of a Zen 2 chip in the wild? We are getting close enough to release date to have some retail level CPU's in test systems. They usually benchmark them using known benchmarking software.

Will the Zen 2 CPU equal to the 2700X which would probably be a 3700X beat the Intel 9900K?
 

Ajay

Diamond Member
Jan 8, 2001
5,071
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Maybe I'm off-base with FinFET-based chips, but from my experience, leaky chips require more current and less voltage at any given clock. Usually the current/voltage curve versus clockspeed on a leaky vs non-leaky chip will put total power usage at any given clockspeed higher for the leaky chip.

If you compare R7 1700s vs. R7 1800x chips, it certainly looks like AMD binned for higher leakage on the 1800x since they can be power hogs, even when running the same clock as a 1700. 1800x chips were more likely to hit 4.0 GHz and higher, though. Silicon Lottery's figures reflected that fact.
Maybe I need to hit the web again for data on FinFETs. I remember we had a lot of discussions here when Intel first came out with Ivy Bridge.
 

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