I'd like to take credit for that theory, but an Anandtech Editor said it's plausible. It explains the anemicness of the leak from last week but also doesn't make sense because such a large cache would have to be fast and be able to constantly flush and update due to how dynamic games are compared to say a static or fixed motion render.
The Traversal coprocessor was BS due to where it was suggested it would be. Additionally, the same person suggested the VRMs and the memory chips would be on a second PCB connected to the main PCB. This is plain wrong on so many levels yet people fell for it. The Game Cache Andrei mentions as a chiplet is also suspect. I don't think it's been done on a B2C product before, but I could be very wrong here. I'm more interested in how AMD are making up for an otherwise anemic card per fairly accurate leaks (accuracy based on prior rumors). If anyone can get Andrei to hop in this thread and clarify, that would be neat. I'd love to learn something new because I didn't think this was possible. I don't have a reddit and refuse to make one.
I should note that the thread was based on a video titled "RDNA 2 Is Monstrous | Insane Cache System & Performance Info - EXCLUSIVE" which is by "R3d G@m!ng T3ch, I've used alternative symbols to prevent SEO improvement. I don't find his videos viable in the least, and I'm skeptical of his so-called sources which may very well be his son's teddy bear collection for all we know. For the moment the idea of using a large cache only chip is right up AMD's alley. I don't believe any of these Youtube or blog charlatans. We have nothing to go on at the moment other than an anemic engineering board that was leaked last week. It's fun to discuss BS.
I haven’t actually seen the stuff about VRMs and memory. Most of the YouTube channels talking about upcoming hardware are complete garbage. They are making a video every day, it seems, even through there hasn’t been much new information in months. They get a lot of views even though they don’t have any new information. I wonder how much money they are making from talking for 20 minutes without any real content.
As to to the actual “rumors”, there is no way they can put GDDR6 on a separate board from the gpu if that is what they were implying. The VRM on a separate board doesn’t make sense either, at least not in the desktop market. There was some rumors about some new power management system in his latest video. The only thing I can think of is that they are making a mezzanine type card that includes gpu and some voltage regulating hardware. That would more likely be a CDNA card, so it isn’t necessarily complete garbage, it just might be for a different product. The GPUs that AMD will be making for their super computer wins could be a mezzanine type boards/packages with VRMs on the gpu board.
If their top end is using a 256-bit bus, then it seems like they need something to compete with Nvidia. That is why I am taking the cache rumor a bit more seriously. Infinity fabric connected chips do not necessarily need to be on the same board, but if they are using such cache die, then they would much more likely be on the same package as the gpu using IFOP style connections. That is much lower power than IFIS off package links. Such a cache die might be reusable for Epyc, so it makes some sense. An Epyc with 128 MB L4 cache chips would be very interesting.
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