I'd like to take credit for that theory, but an Anandtech Editor said it's plausible. It explains the anemicness of the leak from last week but also doesn't make sense because such a large cache would have to be fast and be able to constantly flush and update due to how dynamic games are compared to say a static or fixed motion render.
The Traversal coprocessor was BS due to where it was suggested it would be. Additionally, the same person suggested the VRMs and the memory chips would be on a second PCB connected to the main PCB. This is plain wrong on so many levels yet people fell for it. The Game Cache Andrei mentions as a chiplet is also suspect. I don't think it's been done on a B2C product before, but I could be very wrong here. I'm more interested in how AMD are making up for an otherwise anemic card per fairly accurate leaks (accuracy based on prior rumors). If anyone can get Andrei to hop in this thread and clarify, that would be neat. I'd love to learn something new because I didn't think this was possible. I don't have a reddit and refuse to make one.
I should note that the thread was based on a video titled "RDNA 2 Is Monstrous | Insane Cache System & Performance Info - EXCLUSIVE" which is by "R3d G@m!ng T3ch, I've used alternative symbols to prevent SEO improvement. I don't find his videos viable in the least, and I'm skeptical of his so-called sources which may very well be his son's teddy bear collection for all we know. For the moment the idea of using a large cache only chip is right up AMD's alley. I don't believe any of these Youtube or blog charlatans. We have nothing to go on at the moment other than an anemic engineering board that was leaked last week. It's fun to discuss BS.