Sandy Bridge die-size estimate from photo

[Martimus]

Intel used LLC to connect the graphics Using ring buss to talk . We already know AMD didn't . Intels has true SoC wereas AMD glued there stuff together. and using memory controller . Not even close to being = or the same. Intel has the bandwidth advantage. You can debate till your blue in the face that still won't change anything.

As for Informal find fim at XS and other places. Simple post history tells all.

You have an architecture overview of Llano that shows how the GPU and CPU are connected? Awesome! Please share!

 

[Nemesis 1]

Actually it would appear to be the other way around. We are waiting for you to say something related to what Intel has told us.

Did Intel tell us about fanciful expansion plans on SB's IGP? Or is that just a concoction of your imagination?

Has Intel told us that there will be a 22nm SB? Or is that just a concoction of your imagination?



And we are wondering why you think Intel can get their bandwidth in ways unattainable by AMD.

If you define at the outset of your argument that Intel can do things that AMD can never do then every argument you make following that statement will be a self-fulfilled one but that doesn't make them any more true or valid.

I am not going to take the time to link to what intel said at IDF . But did you listen to all the technical talks as I did . about 7 hours worth . Intel said enough at IDF to were my points are inline with what Intel has said repeatedly. . XS has some very good links to the tech. talks held at IDF . You want the links go and search . The One that was of great interest was on the graphics a real eyeopener . Kantor will likely have a paper on that talk coming shortly.

 

[Nemesis 1]

You have an architecture overview of Llano that shows how the GPU and CPU are connected? Awesome! Please share!

Actually I was looking for you to show me how the GPU and Cpu talk on Llano.

We know how SB does it . You boys stay with AMD and be happy. I will stay with intel and be happy. 4 years now AMD hasn't said the truth 1 time. Zapata demo is what AMD has done nothing but confusion is what they create.

All you need to do is ans the question How does Llano cpu/ gpu talk . With intel its with the LLc using SUPER high bandwidth Ring bus that scales up with every stop added . comparred to what AMD Llano does.

 

[Idontcare]

I am not going to take the time to link to what intel said at IDF . But did you listen to all the technical talks as I did . about 7 hours worth . Intel said enough at IDF to were my points are inline with what Intel has said repeatedly. . XS has some very good links to the tech. talks held at IDF . You want the links go and search . The One that was of great interest was on the graphics a real eyeopener . Kantor will likely have a paper on that talk coming shortly.

This is where history comes into play.

Shall we look at links from Intel on what they had to say about the i740? Larrabee? HDTV? Cellphones? Itanium?

If the point you are trying to make is that Intel uses PR to preach about their grandiose vision and plans then yes I agree there is 100% probability that Intel said they plan to do great things with their IGP on SB.

But until they actually prove they've done it I'm not inclined to fall for it hook-line-and-sinker all over again. My basement is already filled with 5GHz P4's, no room for 24EU SB's at this time.

 

[Martimus]

Actually I was looking for you to show me how the GPU and Cpu talk on Llano.

I don't know how it is done. Why do you expect me to know? I don't work for or with AMD, nor have I had anything to do with the design of the chip.

We know how SB does it . You boys stay with AMD and be happy. I will stay with intel and be happy. 4 years now AMD hasn't said the truth 1 time. Zapata demo is what AMD has done nothing but confusion is what they create.

This is obvious hyperbole, but the same hyperbole is often said about Intel as well. You have been around long enough, that it amazes me that you have no problem taking what AMD says with a grain of salt, but can't seem to do the same with Intel, even though you have been disappointed with their false claims in the past.

All you need to do is ans the question How does Llano cpu/ gpu talk . With intel its with the LLc using SUPER high bandwidth Ring bus that scales up with every stop added . comparred to what AMD Llano does.

I don't think you really understand how a ring-bus works. Having worked on them before, I can tell you it is not "magic" as you say. It introduces additional latency to go with the higher bandwidth, and has other problems as well. Plus it won't increase bandwidth to the system memory, so I don't know why you think it will lower the memory bandwidth bottleneck.

 

[Nemesis 1]

Thats because Intel has delivered time and time again . Ya they had a setback with larrabee. But its not over till the fat lady sings. Same applies to what IDC said .

HDTV what about HDTV

Cell phones what about it. I believe intels 32nm atom will do just fine in cell phones.

Your right Comparing zapata to SB is wrong . As you said a $ 250 chip verses a $20 chip . But I took that down to $100 dollar chip vs. $20 chip.The lowend SB.

So comparing a $6 intel Atom with zapata you will call fair . Thats how it works with you guys.

Wasn't that long ago me and another member here had a go around about tegra Vs. Imagination . I said it was no contest . I won .

I the ring buss I think I understand exactly whats going on . If you added another stop = more latency true . But you failed here again . You also gain bandwidth with every stop . You also failed to mention that both the LLC and ringbuss . scale up with cpu GHZ . So SB at 3ghz will have less bandwidth and latency than at 4ghz, I think I have a good understanding how the LLC and Ring buss work . What happened to ATi ring buss. Thats right AMD bought ATI intel stopped ATI from using intel tech . To me the big big unknown is the system agent.

 

[IntelUser2000]

You have an architecture overview of Llano that shows how the GPU and CPU are connected? Awesome! Please share!

There was an AMD Fusion diagram which showed the CPU and GPU communicating using the on-chip router. The devil is always in the details however.

 

[Nemesis 1]

This is where history comes into play.

Shall we look at links from Intel on what they had to say about the i740? Larrabee? HDTV? Cellphones? Itanium?

If the point you are trying to make is that Intel uses PR to preach about their grandiose vision and plans then yes I agree there is 100% probability that Intel said they plan to do great things with their IGP on SB.

But until they actually prove they've done it I'm not inclined to fall for it hook-line-and-sinker all over again. My basement is already filled with 5GHz P4's, no room for 24EU SB's at this time.

All nice . Lets go back further were AMD reversed engineered intels chip . Theives,

I doubt it will be a 24 eu . as intel will likely have to do more than just add eus to gain performance. Other parts of the IGP would need to be expanded render and such while other parts are removed . Intel has had a ton of time already to prepare for AMDs assault. Why use it till you need it . Thats not smart business . After all Intel is in the business to make money . Amd is in the business to keep intel from being broken up . I rather see AMD gone and intel broken up . Than things will happen .

 

[Idontcare]

Thats because Intel has delivered time and time again . Ya they had a setback with larrabee. But its not over till the fat lady sings. Same applies to what IDC said .

HDTV what about HDTV

Cell phones what about it. I believe intels 32nm atom will do just fine in cell phones.

If you are only going to entirely dismiss Intel's history of failing to meet their own hype then why bother engaging with poster's who clearly understand the history and are bringing it up as a relevant set of facts to the topic?

You are aware of Intel's venture into HDTV, yes?

Intel shows off giant screens

Intel delays first TV chip

Intel kills TV chip plans

And you are aware of Intel's venture into mobilephones circa 2005, yes?

To this you counter "but they tell us things will be different with 32nm atoms".

So your argument for why we should believe the hype surrounding their GPU on SB is because they have made hype about another product that has yet to see the market as well?

"extraordinary claims require extraordinary proof"

In the meantime I hope all this noise you are adding to the thread hasn't drowned out the signal from my post above regarding possible core layout schemes.

 

[Nemesis 1]

This is not a server topic or forum . We know the layout of present SB lowend desktop . The only reason people bring server crap into these threads is because AMD has nothing but magna cores another glue job . I knew the Intel glue job and what people said would come full circle and it has . So now its my turn to talk about glue. Go search I never commented on the intel glue job . Basicly I agreed .

We seen Ats results of a crippled SB . Than lets not forget I have a SB here be it crippled but none the less . I know more about SB performance than most.

Intel 32nm . will do great on cell . I having a hard time with your talking points . You know dam well that wading into to cold water is much more chilling than just jumping in . But wading in gives you option not to go in all the way. Is this not so?

 

[IntelUser2000]

To this you counter "but they tell us things will be different with 32nm atoms".

So your argument for why we should believe the hype surrounding their GPU on SB is because they have made hype about another product that has yet to see the market as well?

I'll wait for Nemesis to answer in his riddle-filled ways as well but I will answer you too. And hopefully I will have to stop here so we can create another thread to talk about this.

1. 32nm Atoms: Whether its the amount of compilers and developer support around x86, or whether its the ability to eventually run everything we have on desktops, x86-based CE and portable devices allow a big differentiation from the ARM-based ones they used to have.

Plus, the x86 TV CE chip based devices will ship, unlike the first attempt in 2005 which never turned into a product. Also back then, their execution sucked comprehensively, even their bread-and-butter MPU division.

2. CPU graphics: If you notice the timeline for their chipset graphics introductions, significant amount of them were delayed. It didn't matter though because back then, they were still emphasizing on the CPU and its was a seperate development.

I knew they had to execute with Clarkdale, or else they would have had to face their CPU getting delayed.

Sandy Bridge is yet another significant development that focuses even more on the GPU side. It's justifiable to believe Intel's GPU will underperform AMD's but the gap grows ever smaller. While Clarkdale could still live with the GPU-only side not working thanks to an MCM, with Sandy Bridge, you can tie the CPU's fate with the GPU's. Delays=feature cuts

Excellent execution required on CPU=Equally excellent execution on GPU=which requires significantly more manpower and resources

 

[Martimus]

So comparing a $6 intel Atom with zapata you will call fair . Thats how it works with you guys.

Nemesis,

Please don't make this personal. My name is Marty, and I am not "you guys". I don't know who "you guys" is, but I would appreciate it if you did not refer to me as "you guys" and make generalized statements about my beliefs. I have not told you what I believe on this subject, so I would appreciate it if you did not voice any assumptions that you make on what my beliefs are. I do not want to have to take this thread off topic over personal issues.

Wasn't that long ago me and another member here had a go around about tegra Vs. Imagination . I said it was no contest . I won .

I have no idea what this has to do with the topic at hand, but again it was not me who said anything about Tegra or Imagination. I don't even know what Imagination is, and I am only vaguely familiar with Tegra. Please don't try to put words in my mouth, since I really do not appreciate that. Also please try to stay on topic, and open a new thread if you feel the need to talk about something off-topic. That way you are more likely to get responses to your inquiries, since the people reading the topic will be expecting that kind of discussion.

I the ring buss I think I understand exactly whats going on . If you added another stop = more latency true . But you failed here again .

Ok, I don't understand what I failed at, or why you felt the need to use that kind of tone at me. I am not sure what I said that you are debunking with your statements, which is why I don't understand my failure. Maybe you are saying that I fail at other parts of my life, in which case I would prefer not to discuss it on this forum. You are free to PM me with complaints about my personal life however.

You also gain bandwidth with every stop . You also failed to mention that both the LLC and ringbuss . scale up with cpu GHZ . So SB at 3ghz will have less bandwidth and latency than at 4ghz, I think I have a good understanding how the LLC and Ring buss work . What happened to ATi ring buss. Thats right AMD bought ATI intel stopped ATI from using intel tech . To me the big big unknown is the system agent.

How exactly do you gain bandwidth at every stop? A true ringbus only has one path, so it doesn't make any sense to gain bandwidth. Maybe you mean as data gets dropped off along the path, that the bandwidth it was taking up gets freed up?

Also, you mention how ATI used a ring bus on the 2900XT and the HD 3870, neither of which was a success. The 4870 was the GPU where they moved back to a more traditional hub architecture, and it helped allow them to ramp up clocks due to the lower power consumption of the communication bus (plus latency went down with the hub design). In the case of ATI, the ring bus was actually a detriment to their design, so using that as an example isnt the best proponent of the benefits of the ring bus design. You can read more about the changes here: http://www.anandtech.com/show/2556/9

 

[Nemesis 1]

If you are only going to entirely dismiss Intel's history of failing to meet their own hype then why bother engaging with poster's who clearly understand the history and are bringing it up as a relevant set of facts to the topic?

You are aware of Intel's venture into HDTV, yes?

Intel shows off giant screens

Intel delays first TV chip

Intel kills TV chip plans

And you are aware of Intel's venture into mobilephones circa 2005, yes?

To this you counter "but they tell us things will be different with 32nm atoms".

So your argument for why we should believe the hype surrounding their GPU on SB is because they have made hype about another product that has yet to see the market as well?

"extraordinary claims require extraordinary proof"

In the meantime I hope all this noise you are adding to the thread hasn't drowned out the signal from my post above regarding possible core layout schemes.

Look IDC , I am fully aware of Intel marketing before core 2 . I never ever said one good word about P4p . P4c is another deal all together. I would love to go against an AMD 64 right now with my online P4c . With more threads available I know who wins and it isn't AMD64. Pick out some 2 or more threaded apps . and lots see who wins . I am ready and willing . So who has AMD 64 thats wants to be spanked, I will hammer the hammer. Don't say threads don't count because thats not what people say now. The times are changed and the Hammer was't as future proof as P4c.

Nemesis, use that "hammer" to whack yourself back on topic. This really isn't a P4c vs A64 type thread. If you want to make that comparison, please feel free to start a new topic on that. This thread is about SandyBridge and it's die size shots, along with accompanying SB information.
Thanks in advance!
Anandtech Moderator - Keysplayr

 

[VirtualLarry]

Look IDC , I am fully aware of Intel marketing before core 2 . I never ever said one good word about P4p . P4c is another deal all together. I would love to go against an AMD 64 right now with my online P4c . With more threads available I know who wins and it isn't AMD64. Pick out some 2 or more threaded apps . and lots see who wins . I am ready and willing . So who has AMD 64 thats wants to be spanked, I will hammer the hammer. Don't say threads don't count because thats not what people say now. The times are changed and the Hammer was't as future proof as P4c.

Are you feeling alright? You think a P4 can go up against an AMD64? Why don't we do it your way, clock for clock, as you prefer to compare CPUs that way I've read. Then we'll see who is the true performer.

 

[Nemesis 1]

OK Clock for clocks is fine . But AMD would likely win more often than not . Which is fine ,
But when BD comes out . It has to be compared clock for clock ,

Bookmarked,

 

[Nemesis 1]

Nemesis,

Please don't make this personal. My name is Marty, and I am not "you guys". I don't know who "you guys" is, but I would appreciate it if you did not refer to me as "you guys" and make generalized statements about my beliefs. I have not told you what I believe on this subject, so I would appreciate it if you did not voice any assumptions that you make on what my beliefs are. I do not want to have to take this thread off topic over personal issues.



I have no idea what this has to do with the topic at hand, but again it was not me who said anything about Tegra or Imagination. I don't even know what Imagination is, and I am only vaguely familiar with Tegra. Please don't try to put words in my mouth, since I really do not appreciate that. Also please try to stay on topic, and open a new thread if you feel the need to talk about something off-topic. That way you are more likely to get responses to your inquiries, since the people reading the topic will be expecting that kind of discussion.



Ok, I don't understand what I failed at, or why you felt the need to use that kind of tone at me. I am not sure what I said that you are debunking with your statements, which is why I don't understand my failure. Maybe you are saying that I fail at other parts of my life, in which case I would prefer not to discuss it on this forum. You are free to PM me with complaints about my personal life however.



How exactly do you gain bandwidth at every stop? A true ringbus only has one path, so it doesn't make any sense to gain bandwidth. Maybe you mean as data gets dropped off along the path, that the bandwidth it was taking up gets freed up?

Also, you mention how ATI used a ring bus on the 2900XT and the HD 3870, neither of which was a success. The 4870 was the GPU where they moved back to a more traditional hub architecture, and it helped allow them to ramp up clocks due to the lower power consumption of the communication bus (plus latency went down with the hub design). In the case of ATI, the ring bus was actually a detriment to their design, so using that as an example isnt the best proponent of the benefits of the ring bus design. You can read more about the changes here: http://www.anandtech.com/show/2556/9

You said this.

How exactly do you gain bandwidth at every stop? A true ringbus only has one path, so it doesn't make any sense to gain bandwidth. Maybe you mean as data gets dropped off along the path, that the bandwidth it was taking up gets freed up?

Now when you read up on intels Ring bus for SB . Than we can continue. The stops are very meaning full and one of you guys did a wonderful job of explaining it with marbles so to speak . Either you haven't read about SB ring bus and WHY its differant than Intels other ring bus. Or you failed to comprehend the design.

 

[Idontcare]

Speaking of marbles, did anyone else notice this bitchen post some poor bastard made way above? Dumbass must have been thinking this was a thread about sandy bridge diemaps or something what a newb

 

[Nemesis 1]

^

When you wrote this you lost me so I gave up on it .


That doesn't accommodate a second memory controller nor the requisite QPI logic for multi-socket support.

If we use the dead space to double the IMC we end up with a chip that is 24.4mm x 9.9mm (242 mm2) with a floorplan that allows for 20mm^2 die area for the QPI and generates 243 chips per wafer.

I not sure what your saying here . Why are we doubling IMC space memory controller. The qpi space should be the only additional space required. Other than adding 2 4 6 more cores.

 

[ilkhan]

Very nice IDC.
I saw, I just was on my way out the door. My response would be how big of a difference is it to Intel if they make 254 or 256 (or etc) chips per wafer? 6 cores w/o graphics would be gulftown sized, and 8 cores are gonna be high enough margin for a slight difference not to matter, yes?

And how are those layouts determined when you don't know how much space each part is going to take? Are the layouts re-evaluated as the design progresses, are blocks moved around? Seems like moving stuff would introduce huge problems with time critical paths. Even as 10mm, the speed of transmission isn't instantaneous.

And I agree with what IntelUser2000 said right after my post, s1155 6-cores, if they exist, will be the wide/short layout used for the 4 cores. It makes sense and it doesn't require changing to ring-bus layout. Nothing is communicated between the system agent and the GPU without going through the ring-bus anyway, so adding a couple cycles of latency (for the 2 extra cores/ring-bus-stops) shouldn't be a problem.

Regarding the 243 and 231 examples, the 231 doesn't have space for the extra PCI-E links on s2011. Makes it even more in favor of the 243. Thanks for the comparison.

I'm at a LAN the rest of the evening, but shall watch this when I can.

 

[Idontcare]

I not sure what your saying here . Why are we doubling IMC space memory controller. The qpi space should be the only additional space required. Other than adding 2 4 6 more cores.

Extra memory controller for those tri and quad channel memory configs.

My response would be how big of a difference is it to Intel if they make 254 or 256 (or etc) chips per wafer? 6 cores w/o graphics would be gulftown sized, and 8 cores are gonna be high enough margin for a slight difference not to matter, yes?

Yeah I intentionally left out any conclusions or opinions from that post that might have conditioned people to think a certain way about the math at play.

My personal take on it is that the die-per-wafer results show that its a wash...meaning chips per wafer alone doesn't make for a compelling decision point when it comes to the layout arrangement of various core SB layouts.

Meaning the layout decisions were likely entirely made to maximize performance, stuff we wouldn't have the data to even make wild-ass guesses about in truth, and likely had little to do with maximizing die per wafer within the range of the ten die or so differences we are seeing here with these crude estimations.

And how are those layouts determined when you don't know how much space each part is going to take? Are the layouts re-evaluated as the design progresses, are blocks moved around? Seems like moving stuff would introduce huge problems with time critical paths. Even as 10mm, the speed of transmission isn't instantaneous.

It's an iterative process of refinement and optimization that continues even after the product is released (albeit to a much smaller degree).

 

[IntelUser2000]

Speaking of marbles, did anyone else notice this bitchen post some poor bastard made way above? Dumbass must have been thinking this was a thread about sandy bridge diemaps or something what a newb

The rumor has it that the person is a moderator.

 

[Edrick]

Ok, back on topic (sort of)

Will the 2C version of SB actually be a full 4C die with 2 cores disabled? Or will it be its own part with a smaller footprint?

On the same note, will the i5 2400 and 2500 be a i7 2600 die with HT disabled and 2mb L3 disabled?

 

[IntelUser2000]

Ok, back on topic (sort of)

Will the 2C version of SB actually be a full 4C die with 2 cores disabled? Or will it be its own part with a smaller footprint?

On the same note, will the i5 2400 and 2500 be a i7 2600 die with HT disabled and 2mb L3 disabled?

No, the 2 core version of Sandy Bridge will have a seperate die entirely. Hyperthreading takes too little space and is a bit complex to make another die just for one without it, and yes it looks like the 6MB L3 versions are 8MB L3 die with 2MB disabled.

Here's my version of the 8 core Sandy Bridge with 20MB L3.

You may be wondering about the big empty space, but some empty space always exist and the center can be filled with a more capable System Agent.

Another version based on Nehalem EX's layout and a much better drawing on my part. Still 20MB L3.

 

[Nemesis 1]

I like your second drawing the best. But it leads me to wonder about the ring buss lay out . I am also cunfused about the 20mb LLC . Where does the extra 4mbs cache come from? As stated many times so far. The cpu die only has 2mb LLC per core. So intel must add 4mb of extra LLC .

You said this

No, the 2 core version of Sandy Bridge will have a seperate die entirely. Hyperthreading takes too little space and is a bit complex to make another die just for one without it, and yes it looks like the 6MB L3 versions are 8MB L3 die with 2MB disabled.


This is the core that has me very suspicious of what intels move will be in the top lowend . The 2 core version can be coupled together to give us 24 eus on one chip . Be they 2 differant cores. Call it intels sli. I suspect this will be intels short ans. for llano the beast of burden. I suspect intel has a beast of burden of its own . Be it pack mule or elephant. This would be intels quik fix. But its possiable intel has a more elaborate approach. As for the 2x core approach. Intel would also need to add more LLC also. Just as they seem to be doing with your 8 core 20mb you designed.
Intel simplely gets rid of 1 system agent and couples everthing together threw the ring buss. I not believing 8mb llc would be enough for this approach. My reasoning being that if intel wants more bandwidth they simply add 2mb more LLC which adds another stop on the bus which adds more bandwidth that graphics like so well. The added latency can be easily hidden . For this to take place Intel only needs a little magic in the system agent

 

[Nemesis 1]

Off topic . Are others having problems staying logged in . I am its really making me angry.