Sandy Bridge die-size estimate from photo

[Nemesis 1]

Well if the 2core with IGP has 4mb cache . 4+4=8mb. Cache. Ring stop and slices has nothing to do with stopping additions of more and differant cores.

http://www.theregister.co.uk/2010/09/16/sandy_bridge_ring_interconnect/

 

[ilkhan]

The L3/"Last Level cache" is divided into 2MB slices, each attached to a core and sharing the ring stop with that core. No core, no cache. Thus no way to add more than 4MB cache to the dual core part. They could do a 6c/12MB cache part, but again I doubt they will until Ivy due to TDP.

 

[Nemesis 1]

You best read the link article. Clearly states cache can be added.

 

[ilkhan]

I've read it. I also looked at the die and *other* more detailed explanations. L3/LLC Cache and cores are connected, in this implementation. For s1155, we get 2MB of L3/LLC per core. Period. That amount may be different for s2011 (I doubt it, the architecture is flexible but die layouts aren't). 2MB/core is pretty fixed for s1155 until Ivy.

 

[IntelUser2000]

There's 95W 6-core Xeon that's clocked at 2.93GHz. I think with the improvements they should be able to do maintain that TDP in Sandy Bridge with the graphics added.

I agree about 2MB/core being fixed for the current layout. They would be able to increase that, but it would require more than simple addition. I'm thinking they'll have to do that with the 8 core parts anyway.

 

[ydnas7]

It's important to note that the SB graphics section doesn't include the memory controller so the comparison isn't completely fair.

i wasn't trying to be fair or precise, the point i was trying to make is that each SB contains the equivalent of a Xbox 360/PS3 graphics engine, in its IGP.
Its not enough for a PC gamer, but it is enough for a mainstream console gamer.

LLano will be different, its proportions of CPU/GPU match the new Xbox 360 chip, except its not speed restricted, and could be 3x larger. I would expect PC games going forward while possible to play pleasantly on SB and consoles, will target LLano as the new PC gaming standard.

 

[ydnas7]

compared to westmere 6C, these Sandybridges are fairly meh, but that is 2 different markets, and Sandybrige EP quad channel/ 6 or 8 core is gulftown's true successor.

compared to Lynnfield (core 15 7xx and i7 etc) SB is both a tock and a tick and a bonus graphics card.

compared to arrandale(core I3 and I5 6xx) SB is even more of a tock, and a very meaningful tick for half the chip.

this is one of the more major releases for intel.

 

[Dark_Archonis]

Rumors are strong that Intel has flexibility with the EUs in Sandy Bridge. Supposedly Intel will take a wait and see approach with Llano and add more EUs to Sandy Bridge models if needed for more competitive integrated graphics performance.

 

[Idontcare]

Rumors are strong that Intel has flexibility with the EUs in Sandy Bridge. Supposedly Intel will take a wait and see approach with Llano and add more EUs to Sandy Bridge models if needed for more competitive integrated graphics performance.

Not saying this isn't/won't be the case but just going based on history and the fact Intel was never really bothered by the fact that their IGP vastly underperformed the competition's IGP performance (AMD and NV) I would be surprised if they really took action against AMD fielding a superior IGP product with eOntario or Llano.

 

[Dark_Archonis]

Not saying this isn't/won't be the case but just going based on history and the fact Intel was never really bothered by the fact that their IGP vastly underperformed the competition's IGP performance (AMD and NV) I would be surprised if they really took action against AMD fielding a superior IGP product with eOntario or Llano.

What you say is true. However, I think there might be something to these rumors simply because with Sandy Bridge Intel is taking integrated graphics much more seriously than before.

 

[Nemesis 1]

^ Couldn't agree more . I have to go what makes the most sense. Intel has stated time and time again upgrading SB cores is an easy task . Sense the design of the present known chip is around now for some time . Intel has had all the time required.

Now an example ONLY. 2600k Is the only SB I believe that has 8mb of LLC . So I not real sure were this 2mb cache a core come from . Clearly All others are not 2mb cache cores. If intel decided to build a IGP core with 2 MB cache and added it to the ring bus. That would give us 8mbcache and another bandwidth bump on the Ring buss. Not saying this is so but it has possiabilities.

IDC makes some fine points about OLD intel. In the past the IGP wasn't a primary concern . As were all very well aware of. But That has changed . IDC thinks Intel doesn't care . I think IDC has gas on this one. AMD announced Fusion . But look at what the 2 companies are bringing to market . Intel Sandy is way better than AMDs fusion . IF bandwidth is a problem with Both these graphics solution . Intels is by far superior. I can't wait to overclock the LLC on sandy . 5 ghz should prove interesting . I keep hereing how AMD fusion will walk all over Intels fusion. Were is AMD going to get the bandwidth for all this performance . Since it was Intel who performed the magic on SB . AMD fusion is nothing more than a glue job same as magna cores.

I see this in the same light as I see fermi . The hype was off the wall . The reality was something else all together. To me this is more about bandwidth than anything else and Intel has the better solution when it comes to bandwidth.

One of the biggest hypers out there goes by the name of informal. He stated many times Zapata would be faster than Intels SB graphics . Now he says only that zapata has better graphics than i5. Its dishonest yet true at the same time . But he knows the differance so its just flat out a lie. He stated many time that AMds PI would be 30-40% faster than . Its alot like the performance differance between the SB and last generation . People here say the improvements are between 15-20% . I will bet everthing I have the average is way higher . Now you can't throw out the high and keep the low . If you keep the low than you must retain the high . We all know what that high is . But you all want to throw that high out. Which is OK by me . I just saying . Its the same as the review sites wanting to put Intels midrange comparred to AMDs high end . Dollar for dollar . LOL . Thats not the metric. The metric is Intels best against AMDs best and its a complete blow out ,not even reasonably close. If you want cheaper buy cheaper but lets stop the BS lies. Intel Vs AMD in gaming . Its not even close . Crank up the res. and test with a game thats not graphics restrained and intel walks all over AMD . Thats future proof. Comparred to AMD.

 

[ilkhan]

^ Couldn't ... bandwidth.

seriously? I seem to recall you were in the last several conversations about sandy, including the rest of this thread. Did you just miss something?

 

[Nemesis 1]

^ No I didn't miss a thing . spit out what ya have to say. I not saying will see a 24 or 18 core eu in jan . Or 2 cores of the 12core eu. But intel has considerable freedom to do as they will with SB . Just because Intel isn't talking about it . The same as they didn't talk about the SB details till IDF. Book mark this thread and when AMD releases super chip . Lets see how intel responseds and how fast they deliver. Intel offers everthing AMD does except tess.

You still haven't nor has anyone else said. Were is AMD going to get the bandwidth for superchip.

 

[Nemesis 1]

Intel has said that 22nm cores will ship from intel between july - dec. They also said they are producing chips @22nm right now . Depending on what intel releases @22nm its possiable intel will be waiting on AMD to release superchip which doesn't have a M/B until april-june 2011. I am betting the 22nm is either SB highend @ 22 or Knights corner. Not Ivy bridge.

 

[ilkhan]

I am betting the 22nm is either SB highend @ 22 or Knights corner. Not Ivy bridge.

I give up.

 

[Nemesis 1]

Don't give up. Because you haven't said anything that relates to what Intel has told us .

I still waiting on were AMD is going to get bandwidth to run super chip.

 

[IntelUser2000]

They can't modify to add more EUs unless the die already includes the extra EUs. It just doesn't work. Now what they can do is add yet another block of GPU. But then they'll have to find methods similar to SLI. Yea... not happening.

 

[ilkhan]

I gave up because sandy on 22nm *IS* Ivy bridge. There are no versions of sandy bridge on a 22nm process not based on the Ivy bridge code name, because Ivy is the overall codename for 22nm. It encompasses various derivative (ivy-EX, ivy-DT, ivy-EP, etc) codenames, but no superior (relevant) codenames. Thus the concept of a 22nm sandy derivative thats not an ivy is...confusing. At best.

IDC (et al), whats your take on a s2011 hex layout looking something like this? I don't know how big the QPI buses are, but...thoughts? Could the empty die space on sandy quads be to have the memory-connection be the right length for the high-volume parts?

 

[IntelUser2000]

That actually looks pretty good. Take a look at how Nehalem-EX is arranged. The significant extra time it takes for Intel to release 6 and 8 core Sandy Bridge parts probably has to do with layout change(but not as long as the true EX versions thanks to less validation time). I think for 6 core, if you just omit the 2 cores from the Nehalem EX die pic, it might be close to how it really looks like.

If they release 6 cores for the Socket 1155 though, they can live with the Gulftown like layout.

 

[Idontcare]

IDC makes some fine points about OLD intel. In the past the IGP wasn't a primary concern . As were all very well aware of. But That has changed . IDC thinks Intel doesn't care . I think IDC has gas on this one. AMD announced Fusion . But look at what the 2 companies are bringing to market .

The point Nemesis is that merely listing possible scenarios does nothing to address the probability of them occurring.

Possibility x Frequency of Occurrence = Probability

Plausibility ∝ Probability

The saying goes "extraordinary claims require extraordinary proof" for a reason.

Intel's history paints a picture for us that supports a position of "I'll believe it when I see it" as far as it goes in assigning the probability of your scenario approaching unity.

AMD has a rich history of doing risky things, from the first to use copper in a mass-produced commodity IC to 64bit x86 to successfully commercializing the IMC as well as pushing multi-core x86 into the consumer world.

I have no problem accepting the position that for AMD the probability of them doing something creative with Fusion is much closer to unity than that of Intel's implementation.

Intel Sandy is way better than AMDs fusion . IF bandwidth is a problem with Both these graphics solution . Intels is by far superior.

Uhm...you know this how? You have Llano in-house?

 

[Idontcare]

Don't give up. Because you haven't said anything that relates to what Intel has told us .

Actually it would appear to be the other way around. We are waiting for you to say something related to what Intel has told us.

Did Intel tell us about fanciful expansion plans on SB's IGP? Or is that just a concoction of your imagination?

Has Intel told us that there will be a 22nm SB? Or is that just a concoction of your imagination?

I still waiting on were AMD is going to get bandwidth to run super chip.

And we are wondering why you think Intel can get their bandwidth in ways unattainable by AMD.

If you define at the outset of your argument that Intel can do things that AMD can never do then every argument you make following that statement will be a self-fulfilled one but that doesn't make them any more true or valid.

 

[Martimus]

AMD fusion is nothing more than a glue job same as magna cores.

Neither Llano nor Ontario are MCM. You can tell from the Ontario die shot how integrated the GPU is to the design (The cores and GPU seem to meld together at weird angles, likely due to the design being automated).

One of the biggest hypers out there goes by the name of informal. He stated many times Zapata would be faster than Intels SB graphics . Now he says only that zapata has better graphics than i5.

I have no idea who informal is, but I sincerely doubt that he stated Zapata would be faster than SB graphics many times, since Zapata was just revealed a couple weeks ago (around the same time the Sandybridge graphics capabilities were revealed). And comparing a ~$20* processor to a ~$250 processor (the i5) doesn't make it seem like he is setting his sights for Zapata too low; at least not to me.

*Pure guess on price by me

 

[Idontcare]

I gave up because sandy on 22nm *IS* Ivy bridge. There are no versions of sandy bridge on a 22nm process not based on the Ivy bridge code name, because Ivy is the overall codename for 22nm. It encompasses various derivative (ivy-EX, ivy-DT, ivy-EP, etc) codenames, but no superior (relevant) codenames. Thus the concept of a 22nm sandy derivative thats not an ivy is...confusing. At best.

IDC (et al), whats your take on a s2011 hex layout looking something like this? I don't know how big the QPI buses are, but...thoughts? Could the empty die space on sandy quads be to have the memory-connection be the right length for the high-volume parts?

Assuming no significant performance impacts are to come from the choice of layout (a false assumption, but let's see where it takes us), the next dominant factor in determining layout will be the question of "how many die per wafer can we get?".

Using Michael Hackerott's wafer-layout simulator with some basic expectations for industry norms (3mm WEE, etc) we arrive at a value of 297 Sandy Bridge chips per 300mm wafer if the die is 20.5mm x 9.9mm (203 mm2) and the usual host of scribe seals and reticle spacing steps, etc.

If we lop off the GPU logic area (~4.7mm wide) that leaves us with a quad-core chip that is 15.8mm x 9.9mm (157 mm2). This layout has potential to generate 380 quad-chips per wafer.

If we add two cores to this, elongating the chip just as the GPU does, then we end up with a hex-core chip that is 22.1mm x 9.9mm (219 mm2) for a layout with the potential of generating 269 hex-core chips.

That doesn't accommodate a second memory controller nor the requisite QPI logic for multi-socket support.

If we use the dead space to double the IMC we end up with a chip that is 24.4mm x 9.9mm (242 mm2) with a floorplan that allows for 20mm^2 die area for the QPI and generates 243 chips per wafer.

Now lets look at the alternative, cutting Sandy down to a 3-core wide chip and then mirroring it so it becomes more of a square than a rectangle.

Such a layout would result in a chip 12.7mm x 19.8mm (252 mm2) with a floorplan that accommodates 25 mm2 die area for QPI and generates 231 chips per wafer.

And last but not least let's consider the 8-core and 10-core possibilities.

Extending the hex-core layou above to 8-cores nets a chip 15.8mm x 19.8mm (313 mm2) with 177 chips per wafer.

Extending to 10-cores nets a chip 19.0mm x 19.8mm (376 mm2) with 151 chips per wafer.

And if they went all-out for a 12-core chip it would be 24.4mm x 19.8mm (483 mm2) for 115 chips per wafer with 4 memory controllers and a whopping 40 mm2 of die area for the engineers to place QPI plus whatever else they'd want on such a mammoth chip.

You'll note I took some liberties with moving the IMC controller to the right a bit in these photoshopped diemaps to minimize the overhang. My justification for doing this is that the logic region to the right of Sandy in these diemaps includes a fair amount of GPU related logic which itself would be removed along with the GPU logic block, giving layout room for optimizing the location of the memory controllers anyways.

(and for those interested, a 2C full 12EU GPU chip would see about 430 chips per wafer)

 

[Nemesis 1]

They can't modify to add more EUs unless the die already includes the extra EUs. It just doesn't work. Now what they can do is add yet another block of GPU. But then they'll have to find methods similar to SLI. Yea... not happening.

Ya I gave that a little thought.

My first thought went to that company that Intel invested in . That does both slew and XF. Hydra . Intel likely has an agreement with them beings its a Israeli product . I an sure the Israeli team that worked on SB has worked with the good people at Hydra. Intel would likely modify the chip to meet its SoC chips. I am not sure what all intel has said about its system agent . But I sure we don't know all of it .

One most also remember The Ring buss handles all communications on these SoC. So intel may have come up with a a Hydra like process for the system agent . But rest assured Intel thought about . Time will tell weather they acted upon it in SB . I recall many said Intel SB wouldn't do CL1.1 or Gl 3.1 Were as I always said they would . Howed that turn out? Intel could likely do software tess . But probably won't until IB. Than do it in hardware . Intel is working very hard to keep the driver stack as small as possiable.

 

[Nemesis 1]

Neither Llano nor Ontario are MCM. You can tell from the Ontario die shot how integrated the GPU is to the design (The cores and GPU seem to meld together at weird angles, likely due to the design being automated).



I have no idea who informal is, but I sincerely doubt that he stated Zapata would be faster than SB graphics many times, since Zapata was just revealed a couple weeks ago (around the same time the Sandybridge graphics capabilities were revealed). And comparing a ~$20* processor to a ~$250 processor (the i5) doesn't make it seem like he is setting his sights for Zapata too low; at least not to me.

*Pure guess on price by me

Intel used LLC to connect the graphics Using ring buss to talk . We already know AMD didn't . Intels has true SoC wereas AMD glued there stuff together. and using memory controller . Not even close to being = or the same. Intel has the bandwidth advantage. You can debate till your blue in the face that still won't change anything.

As for Informal find fim at XS and other places. Simple post history tells all.