Sandy Bridge die-size estimate from photo

[ilkhan]

so 205-220mm^2, is there a transistor count yet?

And, I'm guessing we're calling each of the (highlighted in blue) formations one EU?

 

[IntelUser2000]

Earlier on, it was said to be 1.12 billion transistors.

 

[Idontcare]

And, I'm guessing we're calling each of the (highlighted in blue) formations one EU?
http://img580.imageshack.us/i/2csandybridgediemap.jpg/

I don't really have an answer for that. I expected the 12 EU's to be a larger portion of the GPU die-area. Someone else will have to shed some light on this.

 

[ilkhan]

That was kind've my point. If we're calling that a 12 EU part, that'd have to be a single EU. Im sure its possible that the die shot is only a 6EU part, but I don't know where another 6 EUs would be shoved into the die at, so it seems likely its a full 12 EU. I just wanted to confirm my thinking.

 

[Idontcare]

Yeah, judging from the spaghetti mess that is the synthesized logic area below those 12 discrete units I would have to say I suspect the 6EU gpu's will be a full 12EU logic block but having 6 of the EU's (and associated functionality) disabled.

In other words I don't see them making a smaller chip that has half the GPU die-area for their 6EU SKU's.

 

[IntelUser2000]

You guys suspected it right. The 12 symmetrical portions on the upper part of the GPU are the EUs.

So you can see they can't take out the 6 EUs from there and make a seperate die for it. It won't be worth it. The question is if the EUs will be the only difference between 1 core and the 2 core parts.

Also, it won't be easy to stick that into the Atom and hope it to work. The lack of surrounding I/O and shared cache would hinder its potential. It would probably be a redesign to make it share the Atom's L2 caches or make it work without.

It's also interesting how they will be able to make a seperate die 1 core part. Look at how the blocks are configured. Maybe they'll the cores if they do?

 

[OCGuy]

So...opinions....is this actually a Tock from what you guys can tell?

At first I didn't think so, I thought maybe it was just Nehalem + integrated GPU. But now after seeing some of the more recent performance/layout rumours...

 

[Dark_Archonis]

So...opinions....is this actually a Tock from what you guys can tell?

At first I didn't think so, I thought maybe it was just Nehalem + integrated GPU. But now after seeing some of the more recent performance/layout rumours...

Yes, I would consider it a tock. This is much more than simply Nehalem + integrated GPU.

 

[Nemesis 1]

That was kind've my point. If we're calling that a 12 EU part, that'd have to be a single EU. Im sure its possible that the die shot is only a 6EU part, but I don't know where another 6 EUs would be shoved into the die at, so it seems likely its a full 12 EU. I just wanted to confirm my thinking.

Na thats a 12 EU part . The black areas are eu. The wide ones you see in the center are 2 wide for total of six. Both sides have 3 each. You can see there half the size. So ya its 12 core.

 

[TuxDave]

Na thats a 12 EU part . The black areas are eu. The wide ones you see in the center are 2 wide for total of six. Both sides have 3 each. You can see there half the size. So ya its 12 core.

Yeah, it looks like an 12 EU part to me but you have it a little backwards. The black portions is more likely an SRAM array to store data. Adders/multipliers/whatevers have some structure but they're not that rigid/regular as shown in the die shots. It's most likely the mushy yellow region between the arrays which contain the ALUs.

 

[Nemesis 1]

Ya I could see the green squared section. Just that Those black squares or shaders seems to have 6 smaller units per EU. Thats what caught my attention. But ya a seen the whole EU .

 

[ydnas7]

graphics comparison
Geforce 310M die size 57mm2 260m transistors
ATI 5450 die size 59mm2 292m transistors
XBOX 360 GPU (ATI) 232m transistors (+ EDRAM)
PS3 GPU (nvidia) ~300m transistors (+ CELL)
SB Graphics die size 41mm2 ~300m transistors (xtor increase over Lynnfield ~346m)
prorata the Geforce 310/ATI 5450 and they would be 38mm2 in 32nm process
each SB EU is about 1 mm2

 

[ydnas7]

SB is about 2.5x better than clarkdale graphics on pre-existing games, so it should be reasonable to expect SB optimized games to be about 4x faster than clarkdale.
Ie a game written before SB and designed with ATI/Nvidia in mind will only have a 2.5x increase over clarkdale, but a game written/balance with SB in mind would probably have a 4x slow down on clarkdale.

anyone else note that Nvidia seems to be skipping the production of 60mm2 parts that are DX11 compliant. the lowest DX11 part from Nvidia is the 108 part which is 126mm2. it seems that SB has effectively killed of the future of 60mm2 graphics chips

 

[IntelUser2000]

So...opinions....is this actually a Tock from what you guys can tell?

At first I didn't think so, I thought maybe it was just Nehalem + integrated GPU. But now after seeing some of the more recent performance/layout rumours...

Physical Register Files, uop caches, 256-bit FP, better branch predictor, ring bus, greatly expanded OoO resources, more memory resources.

Actually this is a bigger change than Core 2 had over Core Duo. Almost none of the blocks on the CPU has been left untouched. The efficient integration also means the GPU transistor count is closer to 346 million than 300 million transistors

 

[Nemesis 1]

I beleave its time to wake some people up . Intel said along time ago or rumors say . that Intel will have 2 IGP cores. I believe all IGP core have 12 eu. and we can expect 2 or more cores in SB . As intel repeatedly said at IDF . That the ring bus allows use of many differant cores in their New SB SOC. Read it for yourselves. If I was intel I would only show the 1 core unit. It will be interesting to see how AMD handles the bandwidth of and ondie gpu . I await this miracle of hype.

 

[ilkhan]

wut?

 

[Dark_Archonis]

I beleave its time to wake some people up . Intel said along time ago or rumors say . that Intel will have 2 IGP cores. I believe all IGP core have 12 eu. and we can expect 2 or more cores in SB . As intel repeatedly said at IDF . That the ring bus allows use of many differant cores in their New SB SOC. Read it for yourselves. If I was intel I would only show the 1 core unit. It will be interesting to see how AMD handles the bandwidth of and ondie gpu . I await this miracle of hype.

Hype is one of the only things AMD can rely on now. Looking at the leaked information and diagrams of Bulldozer, I can't see how it will beat or even match Sandy Bridge, let alone 'Sandy Bridge E' and Ivy Bridge. I expect Llano will have an even harder time competing with Sandy Bridge.

 

[Nemesis 1]

wut?

The unit andy tested had 6mb low level catch. The 2400, The 2600K has 8mb of catch . It would be shameful for Intel not to add 1 more IGP in the 130 watt range. 6 cores, 4 cpu 2 igp. Of course the added core would remove unneeded redundancy

 

[ilkhan]

The unit anandtech tested had 6mb L3 cache, the "2400". The "2600K" has 8mb of cache. It would be shameful for Intel not to add a second IGP in the 130 watt range. 6 cores no IGP, 4 core 2 igp. Of course, the added IGP core would remove redundant portions of the GPU.

There won't be any s1155 130W chips. AFAIK it doesn't have the pins to support that much power. Nor will s2011 have GPUs on-die, again AFAIK. Ivy may integrate a second group of EUs; its very likely the number of EUs will go up, but actual dual-GPU is unlikely.

The ability for sandy to go hex on s1155 is limited by power and if Intel really wants to let loose a chip without a GPU on that socket. IIRC the encode/decode engine is within the GPU portion. Unless llano starts kicking ass (very unlikely) I doubt we'll see hex s1155 chips. I hope I'm wrong about that, of course. However, I wouldn't be surprised if the s1366 consumer lineup turns all hex before s2011 gets released. 990X/980/970 would be attractive at the 1k/550/300 price points. Remember that Gulftown IS a smaller die than bloomfield.

At the best of times you can be hard to understand, but both of those posts are worse than normal.

 

[wlee15]

graphics comparison
Geforce 310M die size 57mm2 260m transistors
ATI 5450 die size 59mm2 292m transistors
XBOX 360 GPU (ATI) 232m transistors (+ EDRAM)
PS3 GPU (nvidia) ~300m transistors (+ CELL)
SB Graphics die size 41mm2 ~300m transistors (xtor increase over Lynnfield ~346m)
prorata the Geforce 310/ATI 5450 and they would be 38mm2 in 32nm process
each SB EU is about 1 mm2

It's important to note that the SB graphics section doesn't include the memory controller so the comparison isn't completely fair.

 

[IntelUser2000]

wlee15: The memory controller on the HD5450 is for the GPU only while the one on Sandy Bridge is shared by the two, which means its not completely comparable. Also, needing seperate memory chips on the discrete chips and not needing on on processor graphics parts further complicate the comparison.

The Tech Report says the prospect of having the encoding circuitry on the H2 2011 parts aren't unlikely either.

 

[Idontcare]

At the best of times you can be hard to understand, but both of those posts are worse than normal.

Lol, so true, and I don't think he takes any offense to us noticing this because truth be told we are making the effort to try tocomprehend, digest, contemplate, and respond to his posts.

And you got to admit, we do this because every now and then he lobs a seriously provocative (in a good way) perspective our way that challenges our pre-existing notions of how things are suppose to play out in the market.

The Tech Report says the prospect of having the encoding circuitry on the H2 2011 parts aren't unlikely either.

Are those the 22nm Ivy chips then?

For some reason I am getting a 45nm Lynnfield and 32nm Clarkdale Déjà vu here between 32nm LGA1155 SB and 22nm Ivy.

 

[IntelUser2000]

No, those should still be based on Sandy Bridge.

I think Tock updates are the way to go unless you are looking for specific SKUs.

 

[Nemesis 1]

There won't be any s1155 130W chips. AFAIK it doesn't have the pins to support that much power. Nor will s2011 have GPUs on-die, again AFAIK. Ivy may integrate a second group of EUs; its very likely the number of EUs will go up, but actual dual-GPU is unlikely.

Well I may have overstated the wattage of another IGP core. I may be wrong on this . Correct me if I am wrong. But I believe intel has a 2 core SB with IGP. Now it only seems logical to myself intel could easily use 2 of these cores with 2mb of extra cache for 8mb total . Because of what we already know and don't know about the ring bus. So ya I believe If I thought of this ,Some guy at intel alot smarter than myself seen the possiabilities also. As Intel stated as much at IDF. We can add cores as we please any kind of cores, So ya I think it a great possiabilty. The SB we have wasn't as fast as ATs. SO I really don't yet understand the importance of the the 3rd level cache scaling up with cpu clocking . But from what AT showed and what we got their is a differance in scaling. In a good way. Those 4.9 O/c on sandy on air sounds really impressive. But the unknown is or maybe it is . WERE all 4 cores O/C to that speed If so all the cache would be running at that speed . I very much want to know the scaling as a result of this from the small amout I have to compare to , It should be pretty good . Which in theory should help IGP performance even moreso than cpu performance.

 

[ilkhan]

The ringbus stop for the cache is shared with the core, can't have [cache slice] without the [core]. Dual cores will only have 4MB of L3 on die (and 3MB enabled, for most of them).