Sandy Bridge die-size estimate from photo

[Idontcare]

Credit goes to IntelUser2000 for the links to the photos as well as insightful discussion in pm that prompted me to pull this together.

Fuzzy photo of naked dies of Nehalem (lynnfield), Westmere (clarkdale), and Sandy Bridge (4C): http://hothardware.com/image_popup.aspx?image=big_sandy-bridge-chip.jpg&articleid=14406&t=n

Much clearer image of the same: http://www.semiaccurate.com/forums/showpost.php?p=68237&postcount=26

Rotated, deskewed, and perspective corrected image:

Same image with measurement overlays:

So we are looking at a 4C Sandy Bridge weighing in at a mere ~200-205 mm2

 

[IntelUser2000]

Good, very nice job IDC. :thumbsup:

I just used the ruler on that big pic though, haha.

 

[Riek]

die size seems pretty acceptable this way. might become a big home runner for intel.

 

[ilkhan]

205 seems pretty small (actually it is: 6c gulftown is 248, 4c lynnfield is 296, 4c bloomfield is 263). Is there a way to estimate how much of that is GPU and each core, and then extrapolate to what a 6c with and without GPU would require? It seems with the way the ring bus and die setup works that adding another pair (or more even, if they go back up to the 300mm2 territory) of cores would be relatively simple for Intel to do.

 

[IntelUser2000]

I did some calculations based on the 225mm2 4 core estimate, and it can't be much larger than 350mm2 for the 8 core, graphics-less one, featuring 20MB L3 cache. So they should be able to do the same for 6 core, but with graphics. Since I have seen rumors they might have 6 core + graphics for LGA1155 later, maybe they'll do that after all.

 

[Idontcare]

This should help with the math:

4C sandy sans the GPU logic area would be ~162mm^2

4 more cores would add another 4*17.2 ~= 69mm^2

another 12MB of L3$ would be another 1.5*39.4 ~= 59mm^2

Plus I'm sure they'd add another two QPI's, which I didn't measure but if completely doubled the die area of the non-core non-L3$ (~54mm^2) that would be considerable.

So I tally 162+69+59+54 = 343mm^2 as an upper limit.

 

[Edrick]

4C sandy sans the GPU logic area would be ~162mm^2

4 more cores would add another 4*17.2 ~= 69mm^2

another 12MB of L3$ would be another 1.5*39.4 ~= 59mm^2

Plus I'm sure they'd add another two QPI's, which I didn't measure but if completely doubled the die area of the non-core non-L3$ (~54mm^2) that would be considerable.

So I tally 162+69+59+54 = 343mm^2 as an upper limit.

Didn't Intel (or someone doing a 6C review) mention that 4C seems to be the limit to where a dual memory controller could feed all the cores without bandwidth issues? Hence the talk to a quad channel for LGA2011 and why we only see 6C in the LGA 1366 socket and the tri channel there.

So what size difference are we looking at for a tri/quad mem controller in the above measurements?

 

[ilkhan]

wait, QPI? Why is there QPI on a s1155 chip? I thought part of the point of the IMC and iGPU was removing the need for that bus. It was on clarkdale/arrandale to talk to the gpu/"IMC" die, but thats all on chip for sandy, same as lynnfield.
Edrick: dual DDR3-1600 = triple DDR3-166. IIRC, 1066 is as high as officially supported on bloomfield/gulftown i7 chips (server chips sometimes support 1333, it seems). So bandwidth with dual 1600 wouldn't be a big problem. We all know they chips work fine with faster RAM, but its not official.

 

[IntelUser2000]

When they say 6C needs triple channel, it usually applies to workstations and servers. They probably won't need one for a 6C mainstream part.

IDC: On the GPU side, there's also the interface to the rest of the cores, DMI, and port for display. It looks like it already has two DMI ports, one near the GPU and one near the SCH.

 

[Idontcare]

Didn't Intel (or someone doing a 6C review) mention that 4C seems to be the limit to where a dual memory controller could feed all the cores without bandwidth issues? Hence the talk to a quad channel for LGA2011 and why we only see 6C in the LGA 1366 socket and the tri channel there.

So what size difference are we looking at for a tri/quad mem controller in the above measurements?

The final "fudge number" of 54mm^2 was doubling everything that wasn't explicitly measured as GPU, core, or L3$ in the diemap.

So that would include a doubling of the IMC. It also would include a doubling of some silly stuff too, like the DMI ports as IntelUser pointed out.

wait, QPI? Why is there QPI on a s1155 chip? I thought part of the point of the IMC and iGPU was removing the need for that bus. It was on clarkdale/arrandale to talk to the gpu/"IMC" die, but thats all on chip for sandy, same as lynnfield.
Edrick: dual DDR3-1600 = triple DDR3-166. IIRC, 1066 is as high as officially supported on bloomfield/gulftown i7 chips (server chips sometimes support 1333, it seems). So bandwidth with dual 1600 wouldn't be a big problem. We all know they chips work fine with faster RAM, but its not official.

You are right, sry, wasn't paying attention there for a moment.

Yeah, so we'd need to add in the space for 2x QPI to enable quad-socket configs.

When they say 6C needs triple channel, it usually applies to workstations and servers. They probably won't need one for a 6C mainstream part.

IDC: On the GPU side, there's also the interface to the rest of the cores, DMI, and port for display. It looks like it already has two DMI ports, one near the GPU and one near the SCH.

I'm sure there is a whole host of un-core parts I should be excluding from the die-area that remains once the GPU is gutted...not feeling buzzed enough to dive into just yet Gimme a few hours

 

[Edrick]

Edrick: dual DDR3-1600 = triple DDR3-166. IIRC, 1066 is as high as officially supported on bloomfield/gulftown i7 chips (server chips sometimes support 1333, it seems). So bandwidth with dual 1600 wouldn't be a big problem. We all know they chips work fine with faster RAM, but its not official.

Sorry if this has been documented already, but does SB officially support 1600? I know that was the rumor, but was it ever confirmed? Sorry for the off-topic question.

 

[ilkhan]

Sorry if this has been documented already, but does SB officially support 1600? I know that was the rumor, but was it ever confirmed? Sorry for the off-topic question.

P67 is supposed to have multiplyers up to like DDR3-2166, and DDR3-1600 is confirmed for mobile chips.

 

[tatertot]

Sandy Bridge 4-core is ~225 mm^2

This can be seen most easily from a large photo of the die on the known 37.5 mm square packaging.

http://media.bestofmicro.com/X/E/261698/original/SandyBridge_Desktop_Chip2.jpg


This is also what the leaked CanardPC info claimed.

The 8-core LGA 2011 part should be 350-370 mm^2.

 

[ilkhan]

You are right, sry, wasn't paying attention there for a moment.

Yeah, so we'd need to add in the space for 2x QPI to enable quad-socket configs.

You're still not paying attention I was asking about 6-8 core on s1156, not even touching s2011 for this question.

 

[IntelUser2000]

Sandy Bridge 4-core is ~225 mm^2

This can be seen most easily from a large photo of the die on the known 37.5 mm square packaging.

If you measure the sides though, only math that works out is if the ratio is 37.5:35, meaning that's the package size.

 

[ydnas7]

so 2 Core, 12EU SB chip ~ 150mm
thats about 10% smaller than a propus,
its about 25% smaller of arrandale MCM.
its about 50% larger than wolfdale (107mm)
i think 2 Core SB can go to pentium/celeron markets much better than arrandale could (arrandale being a more premium part for its time)

 

[Idontcare]

so 2 Core, 12EU SB chip ~ 150mm
thats about 10% smaller than a propus,
its about 25% smaller of arrandale MCM.
its about 50% larger than wolfdale (107mm)
i think 2 Core SB can go to pentium/celeron markets much better than arrandale could (arrandale being a more premium part for its time)

Pretty good, might even be as small as 141mm^2.

 

[ilkhan]

141mm2 seems really small since that includes GPU and IMC, which wolfdale doesn't. Good job Intel.

My very crude 6c w/GPU calculation says 265.617mm^2. That's ((12.66/4)*2+20.5)x9.9. You can't *just* add the L3 and core area, since the die is taller than that. I think I asked before but it got lost in the shuffle. Whats the die area below the L3? IMC? PCI-E?

 

[Idontcare]

141mm2 seems really small since that includes GPU and IMC, which wolfdale doesn't. Good job Intel.

My very crude 6c w/GPU calculation says 265.617mm^2. That's ((12.66/4)*2+20.5)x9.9. You can't *just* add the L3 and core area, since the die is taller than that. I think I asked before but it got lost in the shuffle. Whats the die area below the L3? IMC? PCI-E?

Basically a core is 3.15mm wide, and its share of L3$ fits within the width of that shadow.

So to add 2 cores (and L3$) you start with a die that is 20.5mm wide and add 2*3.15 = 6.3mm to its width...making a die that would be 26.8mm wide.

The height stays a constant 9.9mm while we add and remove these cores. That is why there is a blank red-strip in the lower-left corner...that is just unused die space.

So 26.8mm x 9.9mm = 265.3mm

(what you already computed)

The stuff on the bottom appears to be the IMC.

By the way, lots of IDF slides and discussion on high-performance SB over at pc-watch (Goto-san)...google translate doesn't seem to do too bad of a job.

http://pc.watch.impress.co.jp/docs/column/kaigai/20100917_394622.html

 

[ilkhan]

I'd kind've forgotten about pc-watch, thanks for reminding me. Indeed looks like memory interface.

 

[IntelUser2000]

We might actually need to include the so-called "Dead Space" on that PCWatch die pic.

I'm also not sure about Intel just adding 2 more cores side-by-side from the current 6 core layouts. That will obviously change the die size. Look how the Nehalem-EX is layed out.

 

[tatertot]

If you measure the sides though, only math that works out is if the ratio is 37.5:35, meaning that's the package size.

No, the package is 37.5 square.

 

[ydnas7]

Pretty good, might even be as small as 141mm^2.

cut off a further core, make this 1C2T 12EU and it would make a great little big brother to the dual core atom.
(and compress zacate's profitability down to typical amd margin)

 

[Nemesis 1]

Ya I thought that would be a easy fix for intel . But it is possiable intel aimed Oak trail right at that spot.

 

[Idontcare]

cut off a further core, make this 1C2T 12EU and it would make a great little big brother to the dual core atom.
(and compress zacate's profitability down to typical amd margin)

Its possible but remember Atom is more about silly-low production cost and silly-low power consumption.

If these constraints weren't in place then the atom we have today would not be so lacking in the performance-dept, and as such a castrated SB would then not appear to be the "fix" needed for Atom's lackings.

I would be surprised if Intel views Zacate as an Atom competitor. I think AMD found a market opportunity between upper-end Atom capability and lower-end SB capability (with foresight obviously, not hindsight as my demeanor here might imply) and parked eOntario right in that market spot.

Whatever 1C/cut-down stuff Intel could do with SB to compete with Zacate I suppose AMD could also do with Llano to compete with a cut-down SB. Every way I look at it, between eOntario and Llano, AMD is going to have the compelling solution for this market segment this round (2011-2012) imo.