Samsung to build 14nm chips next year

[AtenRa]

20nm is vastly inferior to 22FF.

Because ???

 

[NostaSeronx]

There has been a lot of arguments about FinFETs. The general consensus is you don't go FinFETs.

28-nm non-depleted channel Bulk planar regardless of foundry is vastly superior to 22-nm Intel FinFETs. 20-nm non-depleted channel Bulk planar regardless of foundry is vastly superior to 16/14-nm FinFETs regardless of foundry.

The only reason to go FinFETs are for marketing terms 3D. While, ignoring the inherit incompetence of body biasing issues FinFETs suffer from. Yes, you can design around these issues, but how much R&D are you willing to sacrifice. How much density loss and margin loss can you handle with profit that is so little.

Planar or go home, is what the cheap guys say. These guys pretty much point to three solutions; Depleted channel Bulk planar, FDSOI planar, Graphene channel Bulk/SOI planar.

Following Intel into FinFETs, CNTs, and Tunnels are fruitless.

 

[NTMBK]

There has been a lot of arguments about FinFETs. The general consensus is you don't go FinFETs.

Rubbish. Samsung, GlobalFoundries, TSMC and UMC are all going to FinFET. If that's not consensus then I don't know what is.

 

[NostaSeronx]

Rubbish. Samsung, GlobalFoundries, TSMC and UMC are all going to FinFET. If that's not consensus then I don't know what is.

Samsung/GlobalFoundries(Fab 8) are supporting; 28-nm FDSOI and 14-nm FDSOI, and have said they run faster, and are cheaper to make.

TSMC is restarting its roadmap with a HK-first/MG-last 28-nm FDSOI. Potential licensing to its competitor SMIC, to dominate China.

UMC is in an agreement with Su Volta for DDC for 14-nm and 10-nm.

GlobalFoundries(Fab 1) is testing graphene-channel because of a carbon semiconductor grant from the EU.

The FinFET bum rush is only for technical feat street cred.

 

[NTMBK]

Yes, I'm sure they are sinking billions of dollars of R&D into FinFET for the street cred...

 

[ShintaiDK]

Wasnt there some rule about the nonsense posting? Something about supplying edvidence.

 

[witeken]

Because ???

There has been a lot of arguments about FinFETs. The general consensus is you don't go FinFETs.

28-nm non-depleted channel Bulk planar regardless of foundry is vastly superior to 22-nm Intel FinFETs. 20-nm non-depleted channel Bulk planar regardless of foundry is vastly superior to 16/14-nm FinFETs regardless of foundry.

The only reason to go FinFETs are for marketing terms 3D. While, ignoring the inherit incompetence of body biasing issues FinFETs suffer from. Yes, you can design around these issues, but how much R&D are you willing to sacrifice. How much density loss and margin loss can you handle with profit that is so little.

Planar or go home, is what the cheap guys say. These guys pretty much point to three solutions; Depleted channel Bulk planar, FDSOI planar, Graphene channel Bulk/SOI planar.

Following Intel into FinFETs, CNTs, and Tunnels are fruitless.

Here's some basic semiconductor knowledge:

As transistors have continued to shrink in the past decade, they entered the nanoscale, which is also the domain were quantum phenomena become apparent. Quantum tunneling makes it much harder to turn a nanoscale transistor off, which results in more leakage, etc. So instead, Intel decided to implement a design with a fin surrounded by 3 gates.

Here's a nice presentation: http://youtu.be/NGFhc8R_uO4?t=46m

 

[mrmt]

28-nm non-depleted channel Bulk planar regardless of foundry is vastly superior to 22-nm Intel FinFETs. 20-nm non-depleted channel Bulk planar regardless of foundry is vastly superior to 16/14-nm FinFETs regardless of foundry.

We know of the official AMD shill program, where the wildest fanboys are rewarded with AMD hardware and some even get trips to AMD headquarters, but I never heard of any official SOI shill program. Are you willing to get a SOI wafer to put in your wall?

 

[CHADBOGA]

There has been a lot of arguments about FinFETs. The general consensus is you don't go FinFETs.

No, the general consensus is that you never go full Retard.

 

[AtenRa]

.................

You havent answered the question, why 20nm is vastly inferior to 22FF ????

 

[witeken]

You havent answered the question, why 20nm is vastly inferior to 22FF ????

It is inferior to 22nm, at least from a CPU and SoC POV, because its performance and power consumption are simply worse than 22nm. That's what happens without FF at those nodes. 20nm is claimed to be a measly 20% less power hungry, compared to Intel's 50% claim for 22nm and another 50% for 14nm.

 

[Homeles]

For some reason when I saw AMD mentioned in this my first thought wasn't their APU/GPU products, but their AMD branded memory and SSDs.

Does anyone else think this could be what might get made for them by samsung ?

14nm is a logic node, so no memory.

 

[Phynaz]

You havent answered the question, why 20nm is vastly inferior to 22FF ????

Seriously?

 

[Homeles]

Seriously?

They have their pros and cons. 20nm should be much cheaper, while 22nm should be much higher performing.

 

[witeken]

They have their pros and cons. 20nm should be much cheaper, while 22nm should be much higher performing.

How do you know? Already forgot the numerous claims from a variety of companies that 20nm would not be cheaper then 28nm? Also don't forget the fabless + foundry model's cost vs IDM.

 

[Homeles]

How do you know? Already forgot the numerous claims from a variety of companies that 20nm would not be cheaper then 28nm

Yeah, I had forgotten. Of course, raghu78 will come here with a precompiled pile of garbage and set us all straight on the matter

 

[AtenRa]

It is inferior to 22nm, at least from a CPU and SoC POV, because its performance and power consumption are simply worse than 22nm. That's what happens without FF at those nodes. 20nm is claimed to be a measly 20% less power hungry, compared to Intel's 50% claim for 22nm and another 50% for 14nm.

Where did you see 20nm SOC vs 22nm FF SOC product comparisons ??

 

[AtenRa]

Seriously?

Yea seriously, do you got any numbers to compare the two ??? because in Metal Pitch, TSMC 20nm (64nm) is much better than Intels 22nm FF (90nm)

If anyone else got electrical numbers please post them to see why witeken considers 22nm FF vastly superior to 20nm.

 

[Homeles]

Yea seriously, do you got any numbers to compare the two ??? because in Metal Pitch, TSMC 20nm (64nm) is much better than Intels 22nm FF (90nm)

If anyone else got electrical numbers please post them to see why witeken considers 22nm FF vastly superior to 20nm.

It's not necessary to provide sources for common knowledge.

Intel has had substantial performance leads over its competition for well over a decade. It is you that needs to provide evidence disputing the contrary.

But here, I'll help us both out:
http://www.realworldtech.com/includes/images/articles/iedm10-10.png?71da3d

On every comparison point that exists, TSMC et al. lose out considerably.

 

[witeken]

Yeah, I had forgotten. Of course, raghu78 will come here with a precompiled pile of garbage and set us all straight on the matter

I'm still quite baffled that there is no decrease although the shrink is in line with Moore's law.

 

[jpiniero]

Also don't forget the fabless + foundry model's cost vs IDM.

Intel's spending more than makes up for it though. IIRC, TSMC's 28 nm is way cheaper than Intel's 22 nm.

I'm still quite baffled that there is no decrease although the shrink is in line with Moore's law.

In cost? Because they went to double patterning, that's why. IIRC Intel is also using double at 22 nm, and is rumored to be using quad patterning at 10 nm... which is why I am skeptical about Intel really doing it without EUV. But we will see.

 

[Homeles]

Intel's spending more than makes up for it though. IIRC, TSMC's 28 nm is way cheaper than Intel's 22 nm.



In cost? Because they went to double patterning, that's why. IIRC Intel is also using double at 22 nm, and is rumored to be using quad patterning at 10 nm... which is why I am skeptical about Intel really doing it without EUV. But we will see.

Intel did not use double patterning on 22nm's metal layers. When there's talk about double patterning, it revolves around the lower level metal layers -- confusing as hell, I know.

Regardless, 14nm does use double patterning on the metal, and actually outpaces Moore's Law. There is certainly more to cost/transistor than density.

 

[Nothingness]

But here, I'll help us both out:
http://www.realworldtech.com/includes/images/articles/iedm10-10.png?71da3d

On every comparison point that exists, TSMC et al. lose out considerably.

Doesn't this show that for low power and density TSMC was better than Intel in 2009? Sorry I'm no process specialist :$

Anyway in the end no matter how better your process is, if your product isn't good enough, you lose, and that's what Intel has been experiencing in the mobile market for years, though they are obviously now getting better.

 

[Homeles]

Doesn't this show that for low power and density TSMC was better than Intel in 2009? Sorry I'm no process specialist :$

Anyway in the end no matter how better your process is, if your product isn't good enough, you lose, and that's what Intel has been experiencing in the mobile market for years, though they are obviously now getting better.

For density, yes -- there's no arguing that. But for performance, no. Intel's lag in density is equally met by their competitor's lag in performance. With 14nm, for the first time, Intel will have a lead in both density and performance, and it's very probable this will be true for 10nm as well, although it's too early to say for certain.

It's tough to compare Intel LP to TSMC LP with this chart, since we're given only two data points to compare to -- TSMC's scrapped 32nm node, and their 28nm node. I'll try to highlight what I can.

For INTC 32nm LP, they manage 710 on/0.03 off @1.0V for NMOS, 550/0.03 for PMOS. TSMC's 32nm manages 700 on/1 off, and 380 on/1 off for NMOS and PMOS respectively, at 1.1V. Here, Intel manages higher drive saturation currents, especially for PMOS, has 3/10 of the leakage, all while operating at 0.1V less. It's a blowout, but to be fair, TSMC 32nm never made it to market.

TSMC's 28nm compared to Intel's 32nm is tough, because the voltage difference makes the comparison very indirect. Comparing Intel 32nm to TSMC's 32nm was easy, because Intel manages better drive-to-leakage with less voltage -- if they'd used the same, higher voltage as TSMC, that drive-to-leakage ratio would be even more in Intel's favor.

There's a rule of thumb regarding voltage and its relation idsat and ioff, and its use would allow a rough comparison, but I've forgotten it.

We do have the numbers for Intel's 22nm process, but they're posted in a different format, and again the comparison to TSMC 28nm becomes difficult. I could probably do it, but there'd be a lot of number crunching involved to convert it to the same format used in the big spreadsheet I linked earlier. I'm at work right now but I'll do what I can, but in all likelihood it'll be as big of a blowout, if not larger than 32nm to 32nm was. If I stumble upon the "rule of thumb" conversion method I mentioned earlier, I'll add that as well. I think Kanter mentions it somewhere in his IEDM overviews somewhere.

Sorry, this is complex subject, so if you're not following me, I can hopefully provide more clarification later.

 

[lefty2]

AMD will go FinFET eventually, but not in 2015. You got to remember what Rory Read said atDeustche Bank Conference:

28-nanometer node is going to be the dominant volume of node for the next three, four years....
Now, will we move down to Fins? Yes, absolutely, and our next generation products go there and as we introduce them in 16. But we want to do that as you’re catching the cost curve and the yield curve at the right place so that it makes sense for us.

And when they do go FinFET it'll be with Globalfoundries, not Samsung.