Samsung to build 14nm chips next year

[AtenRa]

Okay, I did the math and 20nm is only a measly 1.23x cheaper (Q4'14).

It is cheaper within a few months in production than a highly depreciated and higher yielded 3+ year old process.

 

[AtenRa]

I dont think you understand the slide at all.

Where do you think 40nm would be on that slide? Even if we scale it back to 40, 28 and 20.

I understand it very well. As for the 40nm, i have no data to say anything at this point. If you have data please post them.

 

[Nothingness]

You need apparently something like 10B revenue.

Where did you get that number from? Masks for 28nm are a few million dollars, so I don't think the impact is that large for higher volumes, but claiming 10B revenues is needed to amortize mask cost looks excessive to say the least

 

[witeken]

This is another good slide to understand why 20nm and 16nm are doing fine.

28nm full production started sometime in Q2-Q3 2011 if im not mistaken, lets say Q4 2011 to have the same quarter as the rest.
According to the above slide, 20nm in Q4 2016 will be cheaper than 28nm in Q4 2015. That means that 20nm will be cheaper only 2 years after the initial production start when 28nm took 4 years to reach the same price.
And then again 16nm at Q4 2017 will reach almost price parity with 28nm of Q4 2015. That means 16nm will only need a single year to reach price parity with 28nm at Q4 2015.

Also, in Q4 2015 28nm products will no be able to reach 20nm performance and power usage. So, although 20nm in Q4 2015 will cost more, 20nm products will command higher prices due to superior performance and lower power usage and ASP will be higher.
Same apply for Q4 2016 when 14/16nm products will be far more advanced than both 28nm and 20nm. So again those 14/16nm products will command higher ASP than the rest at that time.

This is how the industry is working for the last 20-30 years, Intel always degrease its die size of its CPUs but ASP remains the same. AMD and NVIDIA will have to do the same. NVIDIA already did that with Kepler and GK104 two years ago. They introduced a smaller die at higher ASP than before(GF110). They will do the same again at 20nm, they will introduce a smaller die than GM204 at higher ASP.

No. Moore's Law demands more than just price parity or a small decrease. If the price per transistor were the same as in 1965 (all else equal), your phone would now cost some orders of magnitude more than it actually does today.

 

[witeken]

Where did you get that number from? Masks for 28nm are a few million dollars, so I don't think the impact is that large for higher volumes, but claiming 10B revenues is needed to amortize mask cost looks excessive to say the least

I said that I couldn't find it. But it said the cost was 1B so you need 10B revenue.

 

[ShintaiDK]

Where did you get that number from? Masks for 28nm are a few million dollars, so I don't think the impact is that large for higher volumes, but claiming 10B revenues is needed to amortize mask cost looks excessive to say the least

Its the design cost.

Handel said the gate utilization is an issue because of limitations of the design tools and parasitic effects. “The other factor is parametric yields, which are strictly tied into leakage control for the 20nm and of course for the 16nm FinFETs,” he said. “You can break this. Intel has shown that it can be broken and of course that’s an excellent achievement. But, it’s based on very high design costs, potentially $1 billion per design, so you need $10 billion in revenue. It also takes a number of years,” he said. He noted that, in the smartphone market, designs move very fast. “You can’t make that kind of investments in designs.”

http://electroiq.com/petes-posts/20...long-design-cycles-may-delay-20nm-and-beyond/

 

[krumme]

If Intel actually started selling their process on the market we would know to what degree they are actually compettitive with tsmc in a free market situation.

Tsmc that each day prove they can earn money on a market with compettitors. While up til now Intel have only proved they can earn a profit on x86 monopoly like markets but losing huge amount trying to enter arm teritory where there is real competition and every other business segment they tried to enter outside of x86.

Intel have been bragging for years but they havnt put action behind their words but on the contrary lost every bit outside of x86 turf.

Now where would Samsung 20/14nm be in the same competition with tsmc in equal grounds without a beefy suply from ss? Probably the same place as Intel. Its not fit for open competition without heavy subsidies.

Only used for internal use.
Weak ass sauce.

 

[NTMBK]

Its the design cost.



http://electroiq.com/petes-posts/20...long-design-cycles-may-delay-20nm-and-beyond/

I suspect this is why fabs are still showing interest in planar SOI- the higher per-wafer costs vs. lower design costs will make sense for lower volume customers. There was a great graph IDC dug up a while ago on TSMC's distribution of volume:

Seems like the small scale customers make up a heck of a lot of their volume. My guess is that the cheaper design alternative to FinFET is aimed at these guys.

 

[Homeles]

Intel have been bragging for years but they havnt put action behind their words but on the contrary lost every bit outside of x86 turf.

They weren't playing outside of standard x86 turf until very recently. Your post is utter nonsense.

bulk SOI

Those are mutually exclusive

 

[NTMBK]

Those are mutually exclusive

Dammit, I meant planar Thanks for the spot, fixed!

 

[krumme]

Intels pouring money into asml have failed and now hit them in their face.

I think Nosta analysis is actually right here. They are going to fall flat on 10nm for density because of euv tools.

Intels historic disadvantage of density because they have to use the same euv tools as everyone else is now getting worse because asml dev have failed and stagnated.

As usual Intel tried to get monopoly advantage on the euv side by pouring the money into asml - otellini strategy - but forgot gf and amd was not the compettitor any more but instead they met ss as compettitor that have more money and their own for internal use monopoly like products and knew what they were up to.

Now intel get it all in their face. Thats how it is when you meet the big bad guys that knew Intels venture into euv was vulnerable and a sign of weakness.

 

[krumme]

Intel is van der Brink of disaster

 

[krumme]

"There is many ways to shrink"

- the headline for Intels new strategy for density

 

[Erenhardt]

"There is many ways to shrink"

- the headline for Intels new strategy for density

What? Shouldn't it be "There are many ways to shrink"?

 

[witeken]

While up til now Intel have only proved they can earn a profit on x86 monopoly like markets

How do you think they got that monopoly?

 

[krumme]

How do you think they got that monopoly?

It both demands skills to get there but also to defend it. But it was never anythink but monopoly from day one because of x86 license.
And it is a monopoly like market this day on x86 side and only with equal competition can we know who is best. Until now we have only the facts about mobile huge losses for Intel. It might be because of x86 disadvantage - we dont know. The results stand.

 

[Homeles]

Intels pouring money into asml have failed and now hit them in their face.

I think Nosta analysis is actually right here. They are going to fall flat on 10nm for density because of euv tools.

Intels historic disadvantage of density because they have to use the same euv tools as everyone else is now getting worse because asml dev have failed and stagnated.

As usual Intel tried to get monopoly advantage on the euv side by pouring the money into asml - otellini strategy - but forgot gf and amd was not the compettitor any more but instead they met ss as compettitor that have more money and their own for internal use monopoly like products and knew what they were up to.

Now intel get it all in their face. Thats how it is when you meet the big bad guys that knew Intels venture into euv was vulnerable and a sign of weakness.

Are you Daniel Nenni or something? Your bias against Intel is so strong that every other word you write is complete nonsense. This is a technical forum -- get your facts straight. The fact that people such as you are allowed to pretend to have any sort of knowledge here is baffling. The misinformation being spread here is seriously getting out of hand, and the moderation team really needs to do something about it.

EUV is actually shaping up really well, despite all of the delays. The pellicle problem has potentially been solved, and the throughput problem is on track for being solved by 2016. They've even hit their year end goal already of 500 wafers per day, although it was a single system for a single customer.
http://www.asml.com/doclib/investor...40904_2014-09-04_DB_TMT_Conference_London.pdf

Another source confirming EUV's great health:
http://spie.org/x110361.xml

It likely won't be ready for Intel's 10nm node, but by the time their competitors have 10nm out, Intel will be on the cusp of launching 7nm.

And anyway, EUV helps Intel's competitors just as much, if not more. There are a lot of foundries that have been holding off on upgrades in anticipation of next generation lithography.

As far as density goes, it's absolutely laughable that you state that it's " because they have to use the same euv tools as everyone else." First, you mean ArF tools, not EUV tools. Second, it is simply a matter of priorities. Intel historically has not had customers to cater to -- performance has always been the more important problem to solve for them. When Altera's 14nm success story rolls around next year, more people will jump ship to Intel.

 

[krumme]

What? Shouldn't it be "There are many ways to shrink"?

Actually it was "many ways to shrink" but imo its the kind weak talk you do when your usual euv tools just doesnt deliver the numbers.

 

[krumme]

+add Intels investment in Nikon 450mm wafer tech have gone where?

Down the drain obviously - and what a mix of intersts here vs asml. The rest of the mop dont care for 450mm and is nursing their comming14nm fet and non fets.

 

[Homeles]

+add Intels investment in Nikon 450mm wafer tech have gone where?

Down the drain obviously - and what a mix of intersts here vs asml. The rest of the mop dont care for 450mm and is nursing their comming14nm fet and non fets.

FYI: R&D is expensive. The story for 450mm wafers is very simple -- right now, the cost:benefit ratio for investing in 450mm wafer development is not worth it. This will change as time goes on.

And for the record, a rising tide lifts all boats. You should upset that 450mm has been delayed, not grateful because it would mean Intel would get it first. A 30% reduction in cost would have tremendous positive implications on the semiconductor industry, and for the world as a whole. You should be even more upset with EUV's delay, not running around here being joyful because you're happy it harms Intel.

 

[krumme]

When Altera's 14nm success story rolls around next year, more people will jump ship to Intel.

Great. They will have 3 Altera then?

Altera just shows they havnt really started. What they need is another league of business. Altera is just peanuts and just prove my point.

And btw i knew someone would get that example. Well thank you for doing so.

 

[Homeles]

Great. They will have 3 Altera then?

Altera just shows they havnt really started. What they need is another league of business. Altera is just peanuts and just prove my point.

And btw i knew someone would get that example. Well thank you for doing so.

We really need less "glass is half empty" types around here.

 

[krumme]

FYI: R&D is expensive. The story for 450mm wafers is very simple -- right now, the cost:benefit ratio for investing in 450mm wafer development is not worth it. This will change as time goes on.

And for the record, a rising tide lifts all boats. You should upset that 450mm has been delayed, not grateful because it would mean Intel would get it first. A 30% reduction in cost would have tremendous positive implications on the semiconductor industry, and for the world as a whole. You should be even more upset with EUV's delay, not running around here being joyful because you're happy it harms Intel.

Fyi. I think 450mm and euv will get here when the customers will pay for it. And when they pay for it its the right time.
I dont have the slightest personal opinion or feelings of such things.

But the entire idea that it should come here as fast as possible is idiotic as it would move ressources away from other product development. Thats how it works. Failure to see that just shows a narrow mind regarding development.

 

[Homeles]

Fyi. I think 450mm and euv will get here when the customers will pay for it. And when they pay for it its the right time.
I dont have the slightest personal opinion or feelings of such things.

EUV's delay has less to do with money, and more to do with the fact that there's only a single developer for it. The lithography tools market severely lacks competition. If you had two companies playing against each other to push EUV out of the door as fast as possible, we'd have seen it at 32nm like initially planned, or at the least much earlier than 2016.

450mm on the other hand really is something that you can solve by throwing money at it. This would be something that would be really nice if governments would lend a bigger hand to it.

But the entire idea that it should come here as fast as possible is idiotic as it would move ressources away from other product development. Thats how it works. Failure to see that just shows a narrow mind regarding development.

I didn't say that at all, and in fact I stated the opposite.

 

[krumme]

It seems to me the cost/benefit of eg 450mm is well known to the players in the market. A government cant add anything the market cant solve for it selves and bring to product in right time. Funding more basic and risky science development seems in better place. Tech that can help us move the to next level beyond semi conductor be it bio or whatever that is.

Most of the 20-100b brain nerves have each about 10.000 connections and ability to send different signal types. On top of it it constantly evolves in connection with all other brains. A transistor is a meager simple tech compared to that.