Samsung/GloFo EUV 7nm node: gate pitch and interconnect pitch

[witeken]

http://semiengineering.com/the-week-in-review-manufacturing-134/

We already knew from a nice find by Ashraf Eassa that TSMC's 7nm HD SRAM will be 0.54x Intel's 14nm SRAM cell at 0.027um^2, and now we also have some new infos about Samsung and GloFo's 7nm dug up by SemiEngineering.

So here's some context first:

Gate pitch (nm) x Interconnect pitch (nm) = Transistor area (nm^2)

Intel 22nm = 90 * 80 = 7200
TSMC 16nm+ = 80 * 64 = 5120
Samsung 14nm = 78 * 64 = 4992

Intel 14nm = 70 * 52 = 3640
Samsung 10nm = 3145F
TSMC 10nm = 2662F

Intel 10nm = 54 * ?? = 1820F
TSMC 7nm = 1664F
Samsung / GloFo 7nm = *this post* (the article does not further specify between the two companies)

GloFo - Samsung = "44/48" (don't ask me what this means) gate pitch x 36 interconnect pitch = 1.584 / 1.728

As we already knew, they will use SiGe channel strain.

Edit: As I explain here and here, I now estimate that this simple area estimate will produce an area for Intel's 10nm of

Intel 10nm = 54 * 36 = 1.944

They will be able to get a 1.33x higher logic cell density by aggressive design rule enhancement.

 

[carop]

So here's some context first:

Gate pitch (nm) x Interconnect pitch (nm) = Transistor area (nm^2)

GatePitch x FinPitch = Transistor Area

GatePitch x MetalPitch determine cell area.

Intel 10nm = 54 * ?? = 1820F

The problem with that forecast is that Intel's N10 manufacturing process area scaling is not achieved using dimensional scaling only. Have you ever asked yourself why Intel stopped using the simple GatePitch x MetalPitch metric?

Intel will continue to use SADP in their N10 manufacturing process. This means they will deliver metal pitches somewhere around 40nm. As such, Intel's 0.46x scaling is achieved using both dimensional (GatePitch = 54nm, MetalPitch = 40nm) and functional scaling that is also known as fin depopulation.

Fin depopulation means that with the higher drive current of FinFET devices you can use smaller logic cells (metal track scaling). Here is a slide which shows fin depopulation or metal track scaling at work:

 

[witeken]

GatePitch x FinPitch = Transistor Area

GatePitch x MetalPitch determine cell area

In any case gate x metal gives best approximation, that's of course why Intel uses it and everyone reports it.

The problem with that forecast is that Intel's N10 manufacturing process area scaling is not achieved using dimensional scaling only. Have you ever asked yourself why Intel stopped using the simple GatePitch x MetalPitch metric?

Intel will continue to use SADP in their N10 manufacturing process. This means they will deliver metal pitches somewhere around 40nm. As such, Intel's 0.46x scaling is achieved using both dimensional (GatePitch = 54nm, MetalPitch = 40nm) and functional scaling that is also known as fin depopulation.

Fin depopulation means that with the higher drive current of FinFET devices you can use smaller logic cells (metal track scaling). Here is a slide which shows fin depopulation or metal track scaling at work:

You definitely make a compelling argument, and I will certainly take note of this. However, for now I will just continue to assume that they will go for triple patterning to do a 0.65x scaling of the interconnect pitch.

With III-V, Intel could definitely do your depopulation thing, as they have already done to some extent at 14nm because of reduced variability.

But they have not stopped using the gate x metal thing. The last investor meeting was in November last year, so we'll see in a month what they do, and if they give any new things about 10nm. But their lack of metal pitch disclosure is of course open to debate as to why they have done that. In my opinion, this is simply because they do not yet want to disclose their final area scaling.

 

[raghu78]

Thats some impressive tech from IBM.

"the trio of IBM, GlobalFoundries and Samsung technology will also present a paper on 7nm. It will use extreme ultraviolet (EUV) lithography. With EUV, the 7nm technology will feature a contacted polysilicon pitch of 44nm/48nm and metallization pitch at 36nm. “The technology also features dual-strained channels on a thick strain-relaxed buffer (SRB) virtual substrate to combine tensile-strained NMOS and compressively strained SiGe PMOS for enhancement of drive current by 11% and 20%, respectively, versus a common planar HKMG process,” according to an abstract from the companies."

This process is basically IBM 7nm which is what GF 7nm is all about. With a contacted gate pitch of 44/48 nm and a metallization pitch of 36nm this will be the most dense process node in production in early 2019. I think the contacted pitch might be 44nm with EUV + immersion and 48nm with immersion litho only. The contacted pitch of 48nm is still lower than Intel 10nm's contacted pitch of 54nm. This is a high performance process node and it will be interesting to see AMD CPUs designed on this process compete against Intel 10nm CPUs in 2019. IBM / GF will have a denser process than Intel for the first time ever. Intel 7nm is not going to be here before late 2020 / early 2021. Interesting times ahead. I wonder what metric Intel will be using in 2019 to brag that they have the most dense process in the world now that IBM/GF 7nm looks to beat Intel in that metric (Contacted pitch * metallization pitch) .

 

[witeken]

My day today... (here. and here although I'm not the only one recently)

Foruntately it's not yet too late to go to bed . Too bad Idontcare and TuxDave have left just now as the node biz is once again heating up. Homeles would also have got some good input.

(But GloFo/SS/IBM/whoever 7nm is definitely a 7nm foundry node countrary to what I've heard a few times.)

 

[raghu78]

Gate pitch (nm) x Interconnect pitch (nm) = Transistor area (nm^2)

Intel 22nm = 90 * 80 = 7200
TSMC 16nm+ = 80 * 64 = 5120
Samsung 14nm = 78 * 64 = 4992

Intel 14nm = 70 * 52 = 3640
Samsung 10nm = 3145F
TSMC 10nm = 2662F

Intel 10nm = 54 * ?? = 1820F
TSMC 7nm = 1664F
Samsung / GloFo 7nm = *this post* (the article does not further specify between the two companies)

GloFo - Samsung = "44/48" (don't ask me what this means) gate pitch x 36 interconnect pitch = 1.584 / 1.728

As we already knew, they will use SiGe channel strain.

TSMC 16FF+ has a contacted gate pitch of 90nm and a metallization pitch of 64nm.

https://www.semiwiki.com/forum/content/4110-iedm-tsmc-intel-ibm-14-16nm-processes.html

please correct your numbers for 16FF+ and calculation for TSMC 10nm.

 

[witeken]

TSMC 16FF+ has a contacted gate pitch of 90nm and a metallization pitch of 64nm.

https://www.semiwiki.com/forum/content/4110-iedm-tsmc-intel-ibm-14-16nm-processes.html

please correct your numbers for 16FF+ and calculation for TSMC 10nm.

Do they? As we've seen with Apple A9 Intel analysis, they have pretty much same density, SS and TSMC.

And the neat thing is that if I change the 16nm number, I can give TSMC a 2.1x scaling and it will still be a later 10nm number than the current one. So I'm pretty happy with how it is, unless you can refer me to a TSMC paper .

 

[raghu78]

Do they? As we've seen with Apple A9 Intel analysis, they have pretty much same density, SS and TSMC.

And the neat thing is that if I change the 16nm number, I can give TSMC a 2.1x scaling and it will still be a later 10nm number than the current one. So I'm pretty happy with how it is, unless you can refer me to a TSMC paper .

Apple A9 Samsung 96 sq mm . TSMC 104 sq mm. So I don't know where you got the same density idea.

http://www.anandtech.com/show/9686/the-apple-iphone-6s-and-iphone-6s-plus-review/3

btw the semiwiki page I quoted has the info from IEDM presentation about TSMC 16FF+

"Fin patterning and formation on bulk silicon with a 48nm fin pitch is realized using pitch-splitting technique where the fin width is determined by the sidewall thickness of a mandrel. Fin profile and gate profile are carefully co-optimized to balance among the needs to maintain excellent short channel control, to enhance drive current and to reduce parasitic capacitance of the devices. Poly-silicon deposition and gate patterning with a gate pitch of 90nm on the 3-dimensional fin structure is followed by high-K metal gate (HK/MG) RPG process"

Anyway here is a free preview of TSMC paper

https://www.deepdyve.com/lp/institu...y-featuring-2-nd-generation-finfet-INnQf0EUXX

 

[witeken]

Alright, I just prefer to give the benefit of the doubt (cough cough Semiwiki) (except for TTM). The difference between 78 and 80 is too small for die size difference while 90nm too big. Maybe it's got to do with fin size.

 

[Ajay]

Apple A9 Samsung 96 sq mm . TSMC 104 sq mm. So I don't know where you got the same density idea.

http://www.anandtech.com/show/9686/the-apple-iphone-6s-and-iphone-6s-plus-review/3

btw the semiwiki page I quoted has the info from IEDM presentation about TSMC 16FF+

"Fin patterning and formation on bulk silicon with a 48nm fin pitch is realized using pitch-splitting technique where the fin width is determined by the sidewall thickness of a mandrel. Fin profile and gate profile are carefully co-optimized to balance among the needs to maintain excellent short channel control, to enhance drive current and to reduce parasitic capacitance of the devices. Poly-silicon deposition and gate patterning with a gate pitch of 90nm on the 3-dimensional fin structure is followed by high-K metal gate (HK/MG) RPG process"

Anyway here is a free preview of TSMC paper

https://www.deepdyve.com/lp/institu...y-featuring-2-nd-generation-finfet-INnQf0EUXX

The two SOCs don't even have the same layout. So it's pretty hard to speculate about xtor density:

 

[witeken]

The two SOCs don't even have the same layout. So it's pretty hard to speculate about xtor density:

On following graph, I measure 18cm for Samsung A9 and 17cm for TSMC A9, which is a difference of 1.0588. If you multiply that number by 96mm², you get 101.6mm² instead of 104mm², so the 1.0833 difference in density between the raw die sizes is exacerbated. Given that TSMC A8 has even higher density still at 17.5cm, I'm really doubtful gate pitch is 90nm, although WikiChip also says it's that much.

Alright, so they say gate pitch increased by 1.03 compared to 20nm, and 17*1.03 = 17.5(1), which gives credence to both the 90nm number and Intel's analysis (ánd the gate*interconnect approximation).

Since fin pitch is the same 48nm, I guess there's something with Samsung's node that makes it less dense than it theoretically could be unless number is just wrong. Both have 2D layout, but maybe something with the lowest interconnect layers. Maybe Apple used high density 0.07µm² for TSMC and HP 0.08µm² for Samsung. Does TSMC actually have another SRAM size. Given the remarks I've heard from for instance @imported_ats, HD cell used is doubful given its performance.

http://cdn.wccftech.com/wp-content/uploads/2016/09/2015_InvestorMeeting_Bill_Holt_WEB2-page-020.jpg

Edit: A bit interesting to note that the TSMC A8 and A9 have same density before and after normalization. I don't know what to make of that.

 

[Ajay]

My point is that they design rules where different - hence the difference in the layout. There was likely two different teams doing the layout for each process because they were released simultaneously. Because of this, one cannot directly compare two different implementations of the same basic uArch to compute xtor density. There is the raw maximum density of SRAM or logic xtors and then there is a net density number that is affected by design rules in the PDK and individual choices made by a design team (and the tools they use). In other words, the net xtors/mm2 on a given implementation is affected by too many variables to draw conclusions about process node capability.

 

[witeken]

I found a little gem from 2012!

https://youtu.be/_bhEDQzNQ-c?t=21m42s

It seems correct because it correctly predicts the 52nm interconnect pitch for 14nm. So if I take out my ruler, I come up with an estimated 36nm interconnect pitch for Intel 10nm (18nm half pitch) using self-alligned quadruple patterning, which would of course easily explain the delay because it's quite sensible that SAQP is even harder than SADP, which was already an unmanageable complexity.

Only thing that is obviously not correct is the date.

So with that, I get an estimated 0.77 (gate pitch scaling) * 0.69 (metal) = 0.53x scaling. Maybe because of the delays they decided to be ~2nm more aggressive still (which I won't rule out because if you were to remember my previous analysis of Intel's 2 graphs with a ruler, the 2015 version of their density curve was steeper than the 2013 graph and even became steeper than 14nm which has a 0.51x logic scaling), but that's what we can expect realistically. This to be honest is above my estimate of 34-31nm (https://forums.anandtech.com/threads/arm-and-intel-team-up-for-10nm.2483328/#post-38424756). So regular Moore's Law scaling combined with fin depopulation for >2x density.

 

[witeken]

And the plot thickens. Intel's 7nm is now rumored to go into production, not in 2020 or 2022, but in 2019! (The only specified source -- but now there might be 2 -- is "equipment sources" by SE, which might plausibly also be interpreted as Intel will buy 7nm equipment in 2019, which is the same as saying that Intel will buy 10nm equipment in 2016, which they will indeed do in Q4. But in any case interesting development. It's also not completely unlikely that 7nm might launch same time as 10nm++ if that ++node is meant for server products or foundry customers or -S or -X series. Intel also appears to be a little less aggressive at 7nm than 14/10, so that could be a few arguments for the pull-in, but surely there are just as many against )

http://www.eetimes.com/document.asp?doc_id=1330657&piddl_msgid=364357&piddl_msgposted=yes#msg_364357

 

[witeken]

After taking a look at Mark Bohr's slide deck from IDF in August, things are more clear then they are explained in the media, as usual.

At slide 8, you can see gate pitch * logic cell height. You can see that logic cell height does not mean interconnect pitch, because the number nm^2 is far above the ~2000nm^2 you would expect, since the slide only starts at 10.000. So that is how they could come up with that 0.46x number. This is not interconnect pitch, so the interconnect pitch will not be <0.60x to make up for the 0.77x gate pitch scaling. So in terms of pure scaling, it will not be as aggressive as 14nm (0.65x metal).

However, on the next slide 9, you can see that they have done very aggressive "design rule enhancement" to decrease cell height a lot further to get the same scaling trend as 22->14. Based on those logarithmic lines, logic cell area should be about say 2.6x smaller. So by my estimate, those design rules should increase density by a further 1.33x. Of course we don't know if for instance TSMC or Samsung at 10 or 7nm will do a similar trick, so this does kind of go against the simple comparison of interconnect*gate.

In any case, this lines up neatly with my previous post where I estimated 10nm interconnect pitch to be 36nm (https://forums.anandtech.com/thread...and-interconnect-pitch.2489528/#post-38534325).

This also lines up with the forecast that Intel will use III-V and Ge at 10nm to get a massive mobility boost to do this fin depopulation: https://www.youtube.com/watch?v=Kle-pkuQSWY.

https://hubb.blob.core.windows.net/5a741d00-0c8a-45e4-9112-cfe073fe4ed1-published/0d7699d9-605d-4fa1-a61c-694d2a4b96ce/SPCTI01 - SF16_SPCTI01_102f.pdf?sv=2014-02-14&sr=c&sig=v2fw0EpCYkZIxv0N5Jezdm2VTaj0B07QucCC3kLdbV4=&se=2016-10-25T11:10:05Z&sp=r

Edit: The question is of course how Intel can know the area of their 10nm competitors to claim the generational lead, since they probably have to measure this cell area themselves to know how other companies' design rules affect logic density to get apples-apples.

 

[witeken]

GatePitch x FinPitch = Transistor Area

GatePitch x MetalPitch determine cell area


The problem with that forecast is that Intel's N10 manufacturing process area scaling is not achieved using dimensional scaling only. Have you ever asked yourself why Intel stopped using the simple GatePitch x MetalPitch metric?

Intel will continue to use SADP in their N10 manufacturing process. This means they will deliver metal pitches somewhere around 40nm. As such, Intel's 0.46x scaling is achieved using both dimensional (GatePitch = 54nm, MetalPitch = 40nm) and functional scaling that is also known as fin depopulation

See my last post, you are only in part correct. The metal pitch will be 36nm. By the way, I have seen a lower estimate of 36nm for double patterning, although they might use quadruple patterning, I don't know. This was with a k1 value of 0.25.

Edit: And notice that stunning switching energy drop at 10nm (slide 16)! A lot bigger than 22nm or 14nm with the much hyped up finFET! Next year's Cannonlake Core m will blow Apple A11 out of the water! This drop could probably not be done with just another finFET design . So I would say at least quantum well. Slowly the curtain is falling behind Intel's 10nm and it's looking very promising despite the year delay. Gate delay is disappointing, though. I actually would have rather expected a speed improvement from III-V than power.

https://hubb.blob.core.windows.net/5a741d00-0c8a-45e4-9112-cfe073fe4ed1-published/0d7699d9-605d-4fa1-a61c-694d2a4b96ce/SPCTI01 - SF16_SPCTI01_102f.pdf?sv=2014-02-14&sr=c&sig=v2fw0EpCYkZIxv0N5Jezdm2VTaj0B07QucCC3kLdbV4=&se=2016-10-25T11:10:05Z&sp=r

 

[mikk]

Semiwiki published another process comparison.

https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html

 

[raghu78]

Looking at the semwiki comparison TSMC 7nm's main advantage over Intel 10nm and maybe even GF 7nm / Samsung 7nm (though not much is known about both these processes) is the 6 Track library which leads to the world's smallest High density SRAM cell at 0.027 um2. Intel 's HD SRAM cell is 0.0312 um2. TSMC 7nm is going to be a dominant node as they have a roughly 9-12 month time to market lead over GF 7nm and Samsung 7nm. They have an extremely high transistor/sq mm metric due to the availability of a 6 track library. I think for mobile chips that will be the library of choice, though we need to see actual chips like Apple A12 before we can draw conclusions.

For many years we saw Cell Area = Contacted Gate pitch * Minimum Metal pitch as the widely used metric for density comparisons. Now with different track libraries from each of these companies the comparison gets even more nuanced. TSMC 7nm seems to have the highest Transistor / sq mm beating out even Intel 10nm though the comparison is distorted as TSMC 7nm offers 6 track library while Intel 10nm is a 7.56 track library. I am pretty sure TSMC 7nm HPC will use 7.5 track library and there Intel 10nm will have the density adavantage. The dark horse here seems to GF 7nm whose claimed 7nm density scaling of 64% wrt 14nm seems to be very high and could beat out both Intel 10nm and TSMC 7nm for a 7.5 track library.

http://semiengineering.com/to-7nm-and-beyond/

We should have a better idea by year end when more clear data on GF 7nm and Samsung 7nm will be available from presentations at IEDM 2017.

 

[dark zero]

My day today... (here. and here although I'm not the only one recently)

Foruntately it's not yet too late to go to bed . Too bad Idontcare and TuxDave have left just now as the node biz is once again heating up. Homeles would also have got some good input.

(But GloFo/SS/IBM/whoever 7nm is definitely a 7nm foundry node countrary to what I've heard a few times.)

In fact EUV is a TRUE node contrary of FinFet, but it will be the last with the current materials before we start to move on.

 

[Arachnotronic]

GatePitch x FinPitch = Transistor Area

GatePitch x MetalPitch determine cell area.




The problem with that forecast is that Intel's N10 manufacturing process area scaling is not achieved using dimensional scaling only. Have you ever asked yourself why Intel stopped using the simple GatePitch x MetalPitch metric?

Intel will continue to use SADP in their N10 manufacturing process. This means they will deliver metal pitches somewhere around 40nm. As such, Intel's 0.46x scaling is achieved using both dimensional (GatePitch = 54nm, MetalPitch = 40nm) and functional scaling that is also known as fin depopulation.

Fin depopulation means that with the higher drive current of FinFET devices you can use smaller logic cells (metal track scaling). Here is a slide which shows fin depopulation or metal track scaling at work:

Turns out that the bolded was incorrect

 

[Lodix]

Looking at the semwiki comparison TSMC 7nm's main advantage over Intel 10nm and maybe even GF 7nm / Samsung 7nm (though not much is known about both these processes) is the 6 Track library which leads to the world's smallest High density SRAM cell at 0.027 um2. Intel 's HD SRAM cell is 0.0312 um2. TSMC 7nm is going to be a dominant node as they have a roughly 9-12 month time to market lead over GF 7nm and Samsung 7nm. They have an extremely high transistor/sq mm metric due to the availability of a 6 track library. I think for mobile chips that will be the library of choice, though we need to see actual chips like Apple A12 before we can draw conclusions.

For many years we saw Cell Area = Contacted Gate pitch * Minimum Metal pitch as the widely used metric for density comparisons. Now with different track libraries from each of these companies the comparison gets even more nuanced. TSMC 7nm seems to have the highest Transistor / sq mm beating out even Intel 10nm though the comparison is distorted as TSMC 7nm offers 6 track library while Intel 10nm is a 7.56 track library. I am pretty sure TSMC 7nm HPC will use 7.5 track library and there Intel 10nm will have the density adavantage. The dark horse here seems to GF 7nm whose claimed 7nm density scaling of 64% wrt 14nm seems to be very high and could beat out both Intel 10nm and TSMC 7nm for a 7.5 track library.

http://semiengineering.com/to-7nm-and-beyond/

We should have a better idea by year end when more clear data on GF 7nm and Samsung 7nm will be available from presentations at IEDM 2017.

GF has mass production of their 7nm for 1H of 2018 and it is more dense than TSMC's 7nm by just a bit. Samsung has officially said that they will use 10nmLPP and 10nmLPU.

 

[Arachnotronic]

GF has mass production of their 7nm for 1H of 2018 and it is more dense than TSMC's 7nm by just a bit. Samsung has officially said that they will use 10nmLPP and 10nmLPU.

GloFo isn't going into mass production on 7nm in 1H 2018.

 

[Lodix]

GloFo isn't going into mass production on 7nm in 1H 2018.

They advanced the HVM of the 7nm process. Mid 2018 if you want to be more accurate.

http://www.anandtech.com/show/11117/globalfoundries-to-expand-capacities-build-a-fab-in-china

 

[Ajay]

They advanced the HVM of the 7nm process. Mid 2018 if you want to be more accurate.

http://www.anandtech.com/show/11117/globalfoundries-to-expand-capacities-build-a-fab-in-china

The planned increase is

+20% for 14LPP

. Yes, Fab 8 will transition to 7nm, but the timeframe projected is for completion of the 14PP line expansion.

The article also states:

As the company is preparing to start high-volume manufacturing (HMV) of chips using its 7 nm FinFET technology in the second quarter of next year (so, several months ahead of the plan), the actual output of the Fab 8 remains to be seen. Initially, GlobalFoundries plans to use deep ultraviolet (DUV) lithography with quadruple patterning to produce chips using its 7 nm process, but sometime in 2019 it intends to start using extreme ultraviolet (EUV) lithography for a new wave of 7 nm designs. Usage of EUV will not eliminate multi-/quadruple-patterning, but will be used for cirical layers and will thus help to increase output of leading-edge chips. At present, the company does not talk about its 7 nm capacity, but it is logical to assume that the current expansion will have a positive effect on it as well.

So, 2Q18 for the start of 7FF HVM according to GloFo. It not clear that this time frame is actually HVM, since I haven't heard anything about risk manufacturing of 7FF. I'm guess that target is actually risk production with true HVM coming latter in the year (assuming nothing throws off their yields, as happened to Intel on the past two nodes).

 

[raghu78]

GF has mass production of their 7nm for 1H of 2018 and it is more dense than TSMC's 7nm by just a bit. Samsung has officially said that they will use 10nmLPP and 10nmLPU.

GloFo isn't going into mass production on 7nm in 1H 2018.

https://www.globalfoundries.com/new...strys-leading-performance-offering-7nm-finfet

GF's 7nm FinFET technology will be supported by a full platform of foundation and complex intellectual property (IP), including an application-specific integrated circuit (ASIC) offering. Test chips with IP from lead customers have already started running in Fab 8. The technology is expected to be ready for customer product design starts in the second half of 2017, with ramp to risk production in early 2018.

imo GF 7nm will go into risk production by Q2 2018. We should expect actual HVM by early 2019. TSMC 7nm has a 9-12 month lead over GF 7nm. Samsung 7nm is EUV only so that should come later.