Ryzen: Strictly technical

[SirDinadan]

Stilt's excellent memory timing presets

Is there a collection somewhere of these presets?
I managed to save some of it but they are scattered around in txt files and open firefox tabs, it would be cool to have them in one place - Ryzen 1000 / 2000, Raven Ridge, 3200 / 3466 etc.
Does Ryzen APUs benefit from tight timings as well? I haven't benchmarked integrated graphics, but my initial runs didn't show any improvement with a 2200G and mid-range dGPU setup (2400MHz vs 3200MHz auto).

 

[Encrypted11]

Yup.
From the C7H.
Credits to the profile author: The Stilt

Spoiler

https://ibb.co/me59V8
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[Markfw]

Yup.
From the C7H.
Credits to the profile author: The Stilt

Spoiler

https://ibb.co/me59V8
https://ibb.co/hucOq8
https://ibb.co/ce2Oq8
https://ibb.co/mi6uxo
https://ibb.co/nB8JOT
https://ibb.co/gODJOT
https://ibb.co/dQ3UV8
https://ibb.co/e4UExo
https://ibb.co/ciNdOT
https://ibb.co/doGcHo
https://ibb.co/mMbNiT
https://ibb.co/bAMcHo
https://ibb.co/h1QRA8
https://ibb.co/cdGYq8
https://ibb.co/ccjxHo
https://ibb.co/nPBBco
https://ibb.co/gvbBco
https://ibb.co/kKGoOT
https://ibb.co/hRV4xo
https://ibb.co/gTrYq8
https://ibb.co/hpXTOT
https://ibb.co/ijdrco
https://ibb.co/np5hiT
https://ibb.co/garzV8
https://ibb.co/fknpV8
https://ibb.co/mxXZxo
https://ibb.co/gubSHo
https://ibb.co/k4bSHo
https://ibb.co/f9wuxo
https://ibb.co/ccjQ3T

Something like an excel spreadsheet, with each memory, then the appreviation, then the setting would be much easier,.

 

[Elfear]

Not at all.
All DDR4 ICs must be able to sustain up to 1.5V according to JEDEC specs.

Thanks!

 

[elpokor]

Not at all.
All DDR4 ICs must be able to sustain up to 1.5V according to JEDEC specs.

Oh, that certainly solves me a somewhat related enigma. When I googled the IC part number of my two kits of DDR4, oddly enough, the maximum sustained operating voltage according to the specsheets is 1,5V for both Hynix MFR and Samsung B-die ICs. It was a bit mind-boggling, considering the different silicon quality and process node used...

Unfortunately, I don't have access to the JEDEC spec document, so thanks for the clarification!

 

[William Gaatjes]

Hi all.
I am a bit of an odd duck in the lake...


I have the xmp rated 3200MHz ddr4 memory running at 2933MHz with relaxed timings and lower voltage.
I do not need for now absolute maximum speed. I rather prefer a system that is reliable and that i can completely trust.
But i do have a question.
With the program SIV it is possible to read out all the timings of the ddr4 memory sticks.
In the spd data the minimum refresh recovery delay time tRFC1 is set at 260ns.
With the current settings it is 283ns. 23ns more than the minimum required yes ?
I like a little reserve.
Thank you. The stilt for making the ryzen timing checker program.


I tested the memory for about 18 hours with memtest before allowing booting windows. No errors.
Played doom(2016). No issues.
I lowered the VDD to 1.3Volts and increased the amount of clocks required to 18 18 18 40.
I still am going to do some more tests to see if i can get the voltage down to 1.25V.
I do not mind sacrificing some performance if it means i have less things to worry about.
According to aida64, the latency is now 74.1ns.
Read bandwidth is 45,315GB/sec.
Write bandwidth is a 43,834GB/s
Copy is 40,819GB/s.

When looking at these timings, is there something i should be worried about ?

Any remarks ? I am all eyes.

 

[The Stilt]

The default tRFC is 350ns, or 514 CLKs (at 2933MHz) regardless of the DIMMs.

There is plenty to improve with your timings however, ultimately the timings you can use depend on the DRAM IC model.
Lowering the DRAM voltage is pointless, unless you can do so without loosening up the timings.

 

[William Gaatjes]

The default tRFC is 350ns, or 514 CLKs (at 2933MHz) regardless of the DIMMs.

There is plenty to improve with your timings however, ultimately the timings you can use depend on the DRAM IC model.
Lowering the DRAM voltage is pointless, unless you can do so without loosening up the timings.

I see.
My tRFC timing should be fine.

I have G.skill memory : F4-3200C16-4GVK.
From what i have gathered it is either Samsung b-die or e-die.
512Mbit * 8 * chips per rank module.

When it comes to voltage.
I know the absolute maximum ratings are 1.5Volts.
But the recommended voltage for ddr4 is 1.26V max.
Since the ASROCK AB350M does memory voltage in 50mV steps, i put it on 1.3 Volts.
I know i am a bit anal about it. But it i really like to stay close to design specifications when it comes to voltage. The cooler the better. Dram cells forget faster with temperature increases.
Although the memory here does not get hotter than 35C while typing this and it is 25C here.
Temperatures do not get higher than about 40C while gaming.
Although i am already violating jedec specifications with the timings.

It is interesting that the Samsung chips can handle so much increase in clock.
Is for example Samsung rated at jedec DDR4 2666, so easy to overclock ?
I have come to understand that not only the IO clocks increase, but internally the chip runs a t a higher clock as well.
samsung e die and b die is according to the datasheets that i have from Samsung max 2666MHz at jedec spec 2666V (19 19 19) (Jedec datasheet JESD79-4B).
How is it that these chips can handle so much overclock ? Is the Samsung process for dram similar to the Intel 14nm process for the Intel cpu line ?
Meaning, allows much higher clocks than sold for ?


https://en.wikipedia.org/wiki/DDR4_SDRAM#Modules


edit, i misunderstood the tRFC.
I am going to change that setting and see how it runs with a few hours of memtest.
The strangest thing is that i did the test for 10 hours at 2666MHz with those values. And i had no issue.
I see i have to figure out what it does.

 

[Markfw]

Here is my latest attemp to get 3600 stable@1.42v DRAM voltage. Its GSkill Trident-z 3600 15,15,15,35. Do you know of any free software to measure latency ? Aida64 said my trial expired.

 

[William Gaatjes]

Intel has a free tool, but i have not dared trying it on my ryzen system.
https://software.intel.com/en-us/articles/intelr-memory-latency-checker


edit:
Joke , it seems to measure stuff.
but the latency is much higher than what aida gives.
94ns for me.

 

[Markfw]

it comes as a tgz file, and I can't open it.

Edit: I installed aida64 engineer. Even though it says the program has stopped working, I did get the latency to show 68.7ns

 

[William Gaatjes]

it comes as a tgz file, and I can't open it.

Edit: I installed aida64 engineer. Even though it says the program has stopped working, I did get the latency to show 68.7ns

tgz means tar file in gzip file.
The free and excellent program 7zip does it all.
https://www.7-zip.org/
Much better than the build in windows zip unpacker.

 

[stAbb]

Dear William,

If you want to change the settings you have now:

I would start by setting tRAS to 36 (loosest two timings of the ones before, 18+18 in this case) and the tRC to 54 (36+18).
If your tighten or loosen the first timings later and the two loosest timings are odd numbers, I'd add 1 to tRAS so that my tRC ends up as an even number.

As for the secondary timings, I would start by setting tRDDS to 6, tRDDL to 8 and tFAW to (tRDDL*4) 32 or 33 (tRDDL*4+1) if it isn't stable.
If these are stable you can lower it further, for example to 4, 6, 24/25.
If the first set isn't stable on a lower voltage I'd start by changing tRDDL to 9 and tFAW to 36 or 37.

Going to tWTWL and tWR, I never set the 2nd timing lower then the first until I'm done tightening everything else.

I normally start with tRDRD and tWRWR at 4.
However, as I know you have Samsung chips on your memory, I'd start with 3,3 and if stable, I would even try 2, 2.

As for tRFC, even my relatively cheap Hyunda/Hynix memory is completely stable at a tRFC of 300 ns.

As for tCWL, tRT, tRDWR and tWRRD.
As your tRT is 12, I'd tighten the rest to start with.
For example, 16, 12, 6, 3.

I don't really mess with the rest of the timings much, unless one looks really out of place.
Yours look fine to me.

This is simply the way I start out with setting memory timings, no more, no less.
The Stilt has actual experience with the different DDR4 chips, so he knows the odds and inns of the different modules.

With kind regards,
stAbb

Edit:
JEDEC 2133 loads properly for me after a BIOS update. It might indeed have been that GearDownMode was forced through the BIOS and I just didn't realize it at the time.
As a bonus, .vodka explained everything you need to know about it.

 

[.vodka]

On Ryzen, at least on the first gen chips, even if you set tCL to an odd number it will still be loaded as an even number. (tCL +1)

This only happens when you have geardown mode enabled. This requires an even tCL number. If you disable it, then you can set an odd tCL number.


Best performance/more vDIMM required to worst performance/less vDIMM required:

1T command rate, geardown off > "1.5T" CR, geardown on > 2T CR, geardown off


Naturally, geardown mode helps if you're trying to stabilize high speed memory (>3200MHz) and your sticks/IMC/etc can't do pure 1T mode. You can then try to use geardown mode + even tCL as a middle step. If this also fails stress testing or you're not comfortable with how much vDIMM this requires, then well, you can disable geardown mode and use 2T CR.

 

[William Gaatjes]

Dear William,

If you want to change the settings you have now:

I would start by setting tRAS to 36 (loosest two timings of the ones before, 18+18 in this case) and the tRC to 54 (36+18).
If your tighten or loosen the first timings later and the two loosest timings are odd numbers, I'd add 1 to tRAS so that my tRC ends up as an even number.

As for the secondary timings, I would start by setting tRDDS to 6, tRDDL to 8 and tFAW to (tRDDL*4) 32 or 33 (tRDDL*4+1) if it isn't stable.
If these are stable you can lower it further, for example to 4, 6, 24/25.
If the first set isn't stable on a lower voltage I'd start by changing tRDDL to 9 and tFAW to 36 or 37.

Going to tWTWL and tWR, I never set the 2nd timing lower then the first until I'm done tightening everything else.

I normally start with tRDRD and tWRWR at 4.
However, as I know you have Samsung chips on your memory, I'd start with 3,3 and if stable, I would even try 2, 2.

As for tRFC, even my relatively cheap Hyunda/Hynix memory is completely stable at a tRFC of 300 ns.

As for tCWL, tRT, tRDWR and tWRRD.
As your tRT is 12, I'd tighten the rest to start with.
For example, 16, 12, 6, 3.

I don't really mess with the rest of the timings much, unless one looks really out of place.
Yours look fine to me.

This is simply the way I start out with setting memory timings, no more, no less.
The Stilt has actual experience with the different DDR4 chips, so he knows the odds and inns of the different modules.

With kind regards,
stAbb

Edit:
JEDEC 2133 loads properly for me after a BIOS update. It might indeed have been that GearDownMode was forced through the BIOS and I just didn't realize it at the time.
As a bonus, .vodka explained everything you need to know about it.

Thank you. I have to investigate it all first but in all honesty, i am not much of an overclocker.
These sites are quite informative and am reading them to get more familiar with it all.
https://forum-en.msi.com/faq/article/ddr3-memory-timings-explained
http://www.overclock.net/forum/18051-memory/381699-ram-timings-explained.html

 

[William Gaatjes]

The default tRFC is 350ns, or 514 CLKs (at 2933MHz) regardless of the DIMMs.

There is plenty to improve with your timings however, ultimately the timings you can use depend on the DRAM IC model.
Lowering the DRAM voltage is pointless, unless you can do so without loosening up the timings.

I checked both memory profiles again in the dimm spd with siv.
For both 2133MHz(jedec) and 3200MHz(xmp 2.0) the setting for tRFC = minimal 260ns.

-Refresh to Activate Delay / Refresh Cycle Time (tRFC).
Determines the number of clock measured from a Refresh command (REF)
until the first Activate command (ACT) to the same rank

The 283ns is what the motherboard bios sets i assume. I have bios 4.60.
I guess the board bios automatically optimizes the timings ?
Interesting...

 

[stAbb]

Log of mlc.exe running on my system with a 1600x and Hynix AFR modules running at 3200Mhz effectively with tweaked timings @1.365V, so you have something to compare your scores to:

Intel(R) Memory Latency Checker - v3.5
Measuring idle latencies (in ns)...
Memory node
Socket 0
0 72.0

Measuring Peak Injection Memory Bandwidths for the system
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using traffic with the following read-write ratios
ALL Reads : 48478.5
3:1 Reads-Writes : 43212.8
2:1 Reads-Writes : 42621.7
1:1 Reads-Writes : 34691.4
Stream-triad like: 44001.5

Measuring Memory Bandwidths between nodes within system
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using Read-only traffic type
Memory node
Socket 0
0 48477.8

Measuring Loaded Latencies for the system
Using all the threads from each core if Hyper-threading is enabled
Using Read-only traffic type
Inject Latency Bandwidth
Delay (ns) MB/sec
==========================
00000 130.11 47901.7
00002 129.58 47914.6
00008 126.45 47893.8
00015 124.33 47886.8
00050 102.26 47480.5
00100 89.76 34159.8
00200 85.62 20412.1
00300 82.75 14685.2
00400 81.35 11541.8
00500 80.12 9566.4
00700 79.07 7206.4
01000 78.28 5370.3
01300 77.64 4355.2
01700 77.19 3547.8
02500 76.90 2694.2
03500 75.77 2180.9
05000 74.63 1795.7
09000 74.47 1382.3
20000 74.36 1096.5

Measuring cache-to-cache transfer latency (in ns)...
Using small pages for allocating buffers
Local Socket L2->L2 HIT latency 20.8
Local Socket L2->L2 HITM latency 31.4

Edit: my thought process behind the voltages:
JEDEC is the standard but Hyundai tested/rated this voltage for 1.35volts with their XMP profile so I keep close to that.

My board sets my voltages to 1.4 volt for the memory and 1.1 volt for the SOC voltage when I load my XMP profile. I now run tighter timings at higher speed then my XMP profile with 1.365 volts on the memory and 1.0125 volts on the SOC. Even though there is no such thing as a safe voltage, I didn't deviate much from both the SOC voltage nor the ram voltage so it will probably be fine for many years to come. I also bumped both voltages a bit after stress-testing at a lower voltage just to stay on the safe side, stability wise.

 

[William Gaatjes]

I am still wondering where that first high value is coming from.
Here is a log when i tested it @2933 :



Intel(R) Memory Latency Checker - v3.5
Measuring idle latencies (in ns)...
Memory node
Socket 0
0 89.2

Measuring Peak Injection Memory Bandwidths for the system
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using traffic with the following read-write ratios
ALL Reads : 44364.0
3:1 Reads-Writes : 34486.9
2:1 Reads-Writes : 32615.3
1:1 Reads-Writes : 24145.2
Stream-triad like: 37302.3

Measuring Memory Bandwidths between nodes within system
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using Read-only traffic type
Memory node
Socket 0
0 44400.8

Measuring Loaded Latencies for the system
Using all the threads from each core if Hyper-threading is enabled
Using Read-only traffic type
Inject Latency Bandwidth
Delay (ns) MB/sec
==========================
00000 134.76 43856.9
00002 134.61 43854.5
00008 131.12 43876.3
00015 128.84 43855.2
00050 105.81 43521.7
00100 91.85 33567.1
00200 87.24 20049.5
00300 84.10 14393.7
00400 82.17 11326.2
00500 80.60 9389.6
00700 79.21 7078.9
01000 77.92 5283.9
01300 77.27 4292.9
01700 76.79 3498.2
02500 76.14 2667.5
03500 75.94 2152.9
05000 75.39 1768.7
09000 74.66 1369.6
20000 74.51 1090.0

Measuring cache-to-cache transfer latency (in ns)...
Using small pages for allocating buffers
Local Socket L2->L2 HIT latency 20.5
Local Socket L2->L2 HITM latency 34.8

 

[stAbb]

@William Gaatjes

I tried @ 2993mhz 1.2 Volts during a coffee break:

Intel(R) Memory Latency Checker - v3.5
Measuring idle latencies (in ns)...
Memory node
Socket 0
0 78.2

Measuring Peak Injection Memory Bandwidths for the system
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using traffic with the following read-write ratios
ALL Reads : 44483.2
3:1 Reads-Writes : 39604.9
2:1 Reads-Writes : 39024.1
1:1 Reads-Writes : 31747.7
Stream-triad like: 40309.1

Measuring Memory Bandwidths between nodes within system
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using Read-only traffic type
Memory node
Socket 0
0 44481.0

Measuring Loaded Latencies for the system
Using all the threads from each core if Hyper-threading is enabled
Using Read-only traffic type
Inject Latency Bandwidth
Delay (ns) MB/sec
==========================
00000 140.93 43953.4
00002 140.67 43947.9
00008 136.85 43946.5
00015 134.93 43932.5
00050 112.99 43618.8
00100 97.10 34081.1
00200 91.18 20350.6
00300 88.92 14623.5
00400 87.22 11488.1
00500 86.25 9505.8
00700 84.67 7152.2
01000 83.78 5313.6
01300 83.02 4303.2
01700 82.58 3495.5
02500 82.11 2642.6
03500 81.64 2121.0
05000 80.00 1739.1
09000 79.75 1325.8
20000 79.67 1039.2

Measuring cache-to-cache transfer latency (in ns)...
Using small pages for allocating buffers
Local Socket L2->L2 HIT latency 21.0
Local Socket L2->L2 HITM latency 32.5

Geardown mode enabled
Timings:
16-18-18-18-36-54
4-6-24-0-0-4-11-11
0-3-3-420-16-12-6-3

I'm sure this could be tweaked further as I've just punched some numbers into the BIOS.

In your case, I'd start by lowering the primary timings to 16-16-16-16-32-48 and lowering the tRFC to 260ns (381?) before trying anything else.

Hope this helps and with kind regards,
stAbb

 

[msroadkill612]

"As indicated by the Fmax-Vmin curve, the general behavior is almost identical to Summit and Raven Ridge. The scaling and power efficiency is excellent until 3.5GHz and reasonable scaling takes place until 4.0GHz. Beyond this point the voltage scaling is anything but linear, and the CPU is requiring higher voltage in increasingly larger steps to scale further. For example, 4.1GHz requires > 112mV higher voltage"

I agree amd overdoes it with clocking for marketing reasons - vega 64 e.g.

The sensible bottom line for ryzen owners would seem encapsulated in your above quote.

I seem to recall 3933 being regarded as a sweet spot. Is it simple to set such a ceiling in PB2 etc.?

 

[bitxan]

The maximum memory officially supported by ryzen 2700x is DDR4 2933 Mhz, does it represent any danger or would the life expectancy for the cpu shorten the memory?

if 2933 is completely stable ... does it compensate for the work to go up to 3200 or is the difference in performance minimal?

 

[Markfw]

The maximum memory officially supported by ryzen 2700x is DDR4 2933 Mhz, does it represent any danger or would the life expectancy for the cpu shorten the memory?

if 2933 is completely stable ... does it compensate for the work to go up to 3200 or is the difference in performance minimal?

I thought it was 3466, and that what I run my 2 on

 

[bitxan]

maybe I have expressed myself badly, nor do I refer to memory compatibility with the motherboards, I mean that the maximum memory supported by the 2700x according to AMD is 2933 and everything that happens over 2933 is overclocking.

 

[bitxan]

I thought it was 3466, and that what I run my 2 on

maybe I have expressed myself badly, nor do I refer to memory compatibility with the motherboards, I mean that the maximum memory supported by the 2700x according to AMD is 2933 and everything that happens over 2933 is overclocking.

 

[moinmoin]

2933 is the current upper limit of the JEDEC standard. Everything else is "overclocking" as it's not standardized.