Great start Markfw,
If only our boards would auto to timings like these.
If you feel like tweaking some more:
You could try tRFC at 42, that usually works.
If you want to tighten tRDDL/tFAW, set them to 8 and 32.
You could indeed try tRDRDSCL and tWRWRSCL at 3.
tRTP at 13 looks weird to me with tCWL at 14.
I would lower tRTP to 12 and tRDWR to 6 and see what happens.
(I run 16/12/6 for tCWL, tRTP, tRDWR on Hynix AFR memory @ 3200Mhz)
If you feel really brave, you could lower the tWR to 10 and tRDRDSCL and tWRWRSCL to 2, but I'd be surprised if you still get gains without adding stability issues.
At this point you'd be running tRDRDSCL and tWRWRSCL below JEDEC spec at 2133Mhz and tWR at the lowest possible setting on most boards.
Would love to hear if that both works and still improves performance for your memory.
Have fun!
stAbb
Edit, took out mention of tRFC2/4. See The Stilts post.