According to The Stilt the voltage seems to be quite low. So a 140W TDP (not OC'ed) would mean 140 amps at 1V.Socket AM4 leaks, it's said to support 140W+ TDP. (hardly as relevant as the mentioned 95W TDP, but hey...)
According to The Stilt the voltage seems to be quite low. So a 140W TDP (not OC'ed) would mean 140 amps at 1V.Socket AM4 leaks, it's said to support 140W+ TDP. (hardly as relevant as the mentioned 95W TDP, but hey...)
I'm not entertaining the idea, I just mentioned the source.According to The Stilt the voltage seems to be quite low. So a 140W TDP (not OC'ed) would mean 140 amps at 1V.
I have no in-depth information regarding AM4, but based on the known facts it is not too far fetched that the socket itself might be limited to quite low maximum CPU plane power draw.
AM3+ has 940 pins installed and the diameter of each pin is 0.3mm. 170 of these pins are designated for VDDCR (i.e CPU core power). In order to mount 1331 pins to a substrate with same dimensions (40x40mm), they need to reduce the pin pitch from 1.27mm to ~1.07mm. This would mean AM4 would be using essentially a 37x37 pin arrangement instead of the 31x31 used on AM3/+. The resulting pin diameter would be around 0.25mm.
A single pin with 0.3mm diameter (0.07mm² CSA) can carry around 1.49A of current. AMD themselves rate the pins used on AM3/+ and FM2/+ packages for 1.50A in temperatures at or below 30°C. Meanwhile a single pin with 0.25mm diameter (0.049mm² CSA) can carry around 1.15A.
On AM4 many of the pins will be reserved for display outputs and peripherals, while AM3/+ socket did not use any for these purposes. Additionally the common socket design dictates that the socket must support APUs, which means that there must be a high current secondary power plane available.
Even the current generation iGPUs found in Steamroller and Excavator APUs can consume excess 40W at stock and significantly more when overclocked. This means that on AM4 there must be at least 150 (75 VDD_SoC, 75 VSS) reserved for the secondary power plane alone (incl. safety margins). On AM4 CPUs VDD_SoC most likely powers the CNB interface (core northbridge and possibly the L3 cache).
Despite I don't expect first generation Zen CPUs to have basically any margin left for overclocking, I certainly hope AMD hasn't made too grave compromises when designing the socket infrastructure.
Do you have a source on pin diameter for am4?I have no in-depth information regarding AM4, but based on the known facts it is not too far fetched that the socket itself might be limited to quite low maximum CPU plane power draw.
AM3+ has 940 pins installed and the diameter of each pin is 0.3mm. 170 of these pins are designated for VDDCR (i.e CPU core power). In order to mount 1331 pins to a substrate with same dimensions (40x40mm), they need to reduce the pin pitch from 1.27mm to ~1.07mm. This would mean AM4 would be using essentially a 37x37 pin arrangement instead of the 31x31 used on AM3/+. The resulting pin diameter would be around 0.25mm.
Do you have a source on pin diameter for am4?
You can keep or even use 0.4mm pins with less space in between.
I estimated the AM4 pin diameter based on the increase in pin count over AM3+ (940 to 1331).
Sure, you can reduce the space between the pins but after that it is pretty hard to make the socket itself. Currently the space between the pins is 0.24mm (including the pin solder joint / base).
how are AMD cpus in general for overclocking?
AMD Vishera: 8.7GHzIt's more down to the architecture than a company for OC if I'm not mistaken.
Hell, I'd be fine with a six or eight core Phenom II, so long as AMD fixes the bloody draw call deficit with their chipsets.
Sandybridge performance (absolute worst case scenario, mind) + eight cores (16 threads?) + lower power + fixed draw call deficit...Yep, I'd buy that.
Is's another thread but it seems relevant:
http://forums.anandtech.com/showthread.php?t=2469531
These results could easily be the same exact scores for the incoming Zen, at stock ~3GHz, so even assuming a strict ~4GHz wall for overclocks the chip might be really good in games and single threaded tasks.
Yet... I'm comparing it to 32nm Sandy Bridge "dinoasurs" here, the only advantage a 2016-17 chip would have is better motherboard/features and lower power?
So what would you guys say of Zen if it performed exactly like this?
It was April fool article. And your info is right. The ES clock is low.Question: is it possible that AMD sends ES with different clocks?
I saw that report from bitsandchips about Zen ES having 3GHz but we're supposed to get Summit Ridge ES next week and the info AMD sent us last month suggests it's a lower clock.
I've always said that a Llano based Phenom III would have been more palatable than the Bulldozer experiment. Take Llano, lop off the iGPU and slap on an L3 alongside 2/4 more cores and you've got a pretty competitive chip at that point in time. Even without the L3, Llano tended to at worst hang with Deneb if not show modest gains. It wouldn't be much of stretch to believe Llano would have seen similar gains when paired an L3 as well. Some more tweaks here or there and the eventual shift to 28nm would have kept the ship afloat until Zen came around. Sure, these chips would have never touched i7s, but neither did Bulldozer. Bulldozer didn't really even payoff from a tech side either, as Zen seems to have more in common with the K7/8/10 lineage than it does Zen.
There is a caverat. The SB in question got 20MB cache. Try reduce it to say 8MB and remove the quadchannel. Quite different performance.
Thevenin has been exceptionally trust worthy and generally critical of SR EX etc, he is hardly an AMD pet. He works for a OEM ( has never said which one) and says they have them.Personally I don't believe that AMD has sent Zen silicon to anywhere yet.
except its 8mb per compute unit, so 16mb L3 in total for a 8 core chip. You will also have DDR4 vs DDR3 so quad channel doesn't off that much of a benefit. These fundamental mistakes aren't looking good for when you finally grace us with your wisdom and give us a detailed analysis of all the architectural mistakes AMD have made with Zen......................
Its really going to be hard for you if Zen isn't a top chip.
You better hope that the informed sources are wrong. Because its looking quite bad for Zen at the moment.
Personally I don't believe that AMD has sent Zen silicon to anywhere yet. The motherboard manufacturers do need AM4 APUs / CPUs in order to make their AM4 boards, but Bristol Ridge (Carrizo) chips can be used for that purpose.
The clocks on the alleged Zen "A0" part don't tell much really, even if they were true. Nowdays the manufacturers only make new, major die revisions if they absolutely have to (in order to fix errata, which cannot be fixed thru µcode). Things were different back in the day, when both AMD and Intel released steppings to improve the characteristics of the design (power consumption and scaling).
Usually the prototype chips have higher than usual safety margins (for obvious reasons), so the initial silicon revisions can clock just as high as the final ones.
Recently AMD has done very few major die revisions between the initial tape out and the release:
Orochi:
OR-A0 = 3.6GHz (initial)
OR-B0 = 4.1GHz
OR-B2F = 4.3GHz (release, +19.4%)
Trinity:
TN-A0 = 4.1GHz (initial)
TN-A1 = 4.2GHz (release)
Carrizo:
CZ-A0 = 3.4GHz (initial)
CZ-A1 = 3.4GHz (release)
Generation 1 Bulldozer was an exception, since it required four major steppings and several minor revisions before it was ready for release (still had major errata in it).
For example, Stoney Ridge launched with it's initial die revision (A0).
I wont care, i'll just do what i have done with bulldozer try and learn where the failings are.
Your the one who feels the need to push an agenda, im just asking you to backup it up with a shred of anytihng.
by informed sources you mean voices in your head right. There has been what i would call one credible posting around Zen and only a special flower like you could take it negatively........