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New Zen microarchitecture details

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CentroX

Senior member
Apr 3, 2016
344
149
116
I am building a new computer this fall.

+AM4 asus motherboard
+Summit Ridge CPU
+16GB DDR4 2400 RAM
+Polaris GPU
 

The Stilt

Golden Member
Dec 5, 2015
1,709
3,057
106
I have no in-depth information regarding AM4, but based on the known facts it is not too far fetched that the socket itself might be limited to quite low maximum CPU plane power draw.

AM3+ has 940 pins installed and the diameter of each pin is 0.3mm. 170 of these pins are designated for VDDCR (i.e CPU core power). In order to mount 1331 pins to a substrate with same dimensions (40x40mm), they need to reduce the pin pitch from 1.27mm to ~1.07mm. This would mean AM4 would be using essentially a 37x37 pin arrangement instead of the 31x31 used on AM3/+. The resulting pin diameter would be around 0.25mm.

A single pin with 0.3mm diameter (0.07mm² CSA) can carry around 1.49A of current. AMD themselves rate the pins used on AM3/+ and FM2/+ packages for 1.50A in temperatures at or below 30°C. Meanwhile a single pin with 0.25mm diameter (0.049mm² CSA) can carry around 1.15A.

On AM4 many of the pins will be reserved for display outputs and peripherals, while AM3/+ socket did not use any for these purposes. Additionally the common socket design dictates that the socket must support APUs, which means that there must be a high current secondary power plane available.

Even the current generation iGPUs found in Steamroller and Excavator APUs can consume excess 40W at stock and significantly more when overclocked. This means that on AM4 there must be at least 150 (75 VDD_SoC, 75 VSS) reserved for the secondary power plane alone (incl. safety margins). On AM4 CPUs VDD_SoC most likely powers the CNB interface (core northbridge and possibly the L3 cache).

For AM4 I expect to see around 2.5:1 ratio in VDDCR and VDD_SoC power pins. On AM3+ the ratio was 12.1:1 and on FM2+ 3.333:1.

Despite I don't expect first generation Zen CPUs to have basically any margin left for overclocking, I certainly hope AMD hasn't made too grave compromises when designing the socket infrastructure.
 
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CentroX

Senior member
Apr 3, 2016
344
149
116
I have no in-depth information regarding AM4, but based on the known facts it is not too far fetched that the socket itself might be limited to quite low maximum CPU plane power draw.

AM3+ has 940 pins installed and the diameter of each pin is 0.3mm. 170 of these pins are designated for VDDCR (i.e CPU core power). In order to mount 1331 pins to a substrate with same dimensions (40x40mm), they need to reduce the pin pitch from 1.27mm to ~1.07mm. This would mean AM4 would be using essentially a 37x37 pin arrangement instead of the 31x31 used on AM3/+. The resulting pin diameter would be around 0.25mm.

A single pin with 0.3mm diameter (0.07mm² CSA) can carry around 1.49A of current. AMD themselves rate the pins used on AM3/+ and FM2/+ packages for 1.50A in temperatures at or below 30°C. Meanwhile a single pin with 0.25mm diameter (0.049mm² CSA) can carry around 1.15A.

On AM4 many of the pins will be reserved for display outputs and peripherals, while AM3/+ socket did not use any for these purposes. Additionally the common socket design dictates that the socket must support APUs, which means that there must be a high current secondary power plane available.

Even the current generation iGPUs found in Steamroller and Excavator APUs can consume excess 40W at stock and significantly more when overclocked. This means that on AM4 there must be at least 150 (75 VDD_SoC, 75 VSS) reserved for the secondary power plane alone (incl. safety margins). On AM4 CPUs VDD_SoC most likely powers the CNB interface (core northbridge and possibly the L3 cache).

Despite I don't expect first generation Zen CPUs to have basically any margin left for overclocking, I certainly hope AMD hasn't made too grave compromises when designing the socket infrastructure.
how are AMD cpus in general for overclocking?
 

Erenhardt

Diamond Member
Dec 1, 2012
3,251
105
101
I have no in-depth information regarding AM4, but based on the known facts it is not too far fetched that the socket itself might be limited to quite low maximum CPU plane power draw.

AM3+ has 940 pins installed and the diameter of each pin is 0.3mm. 170 of these pins are designated for VDDCR (i.e CPU core power). In order to mount 1331 pins to a substrate with same dimensions (40x40mm), they need to reduce the pin pitch from 1.27mm to ~1.07mm. This would mean AM4 would be using essentially a 37x37 pin arrangement instead of the 31x31 used on AM3/+. The resulting pin diameter would be around 0.25mm.
Do you have a source on pin diameter for am4?
You can keep or even use 0.4mm pins with less space in between.
 

The Stilt

Golden Member
Dec 5, 2015
1,709
3,057
106
Do you have a source on pin diameter for am4?
You can keep or even use 0.4mm pins with less space in between.
I estimated the AM4 pin diameter based on the increase in pin count over AM3+ (940 to 1331).

Sure, you can reduce the space between the pins but after that it is pretty hard to make the socket itself. Currently the space between the pins is 0.24mm (including the pin solder joint / base).
 

Erenhardt

Diamond Member
Dec 1, 2012
3,251
105
101
I estimated the AM4 pin diameter based on the increase in pin count over AM3+ (940 to 1331).

Sure, you can reduce the space between the pins but after that it is pretty hard to make the socket itself. Currently the space between the pins is 0.24mm (including the pin solder joint / base).
If it would be a problem they will surely make a bigger socket. They manage HBM microbumps, surely they will find a workaround the lacking 0,05mm

It is easier to fab smaller joint than to straighten bent gold hairs.
 

SAAA

Senior member
May 14, 2014
471
80
91
Is's another thread but it seems relevant:

http://forums.anandtech.com/showthread.php?t=2469531

These results could easily be the same exact scores for the incoming Zen, at stock ~3GHz, so even assuming a strict ~4GHz wall for overclocks the chip might be really good in games and single threaded tasks.

Yet... I'm comparing it to 32nm Sandy Bridge "dinoasurs" here, the only advantage a 2016-17 chip would have is better motherboard/features and lower power?

So what would you guys say of Zen if it performed exactly like this?
 

MajinCry

Platinum Member
Jul 28, 2015
2,488
557
136
Hell, I'd be fine with a six or eight core Phenom II, so long as AMD fixes the bloody draw call deficit with their chipsets.

Sandybridge performance (absolute worst case scenario, mind) + eight cores (16 threads?) + lower power + fixed draw call deficit...Yep, I'd buy that.
 

nismotigerwvu

Golden Member
May 13, 2004
1,568
33
91
Hell, I'd be fine with a six or eight core Phenom II, so long as AMD fixes the bloody draw call deficit with their chipsets.

Sandybridge performance (absolute worst case scenario, mind) + eight cores (16 threads?) + lower power + fixed draw call deficit...Yep, I'd buy that.
I've always said that a Llano based Phenom III would have been more palatable than the Bulldozer experiment. Take Llano, lop off the iGPU and slap on an L3 alongside 2/4 more cores and you've got a pretty competitive chip at that point in time. Even without the L3, Llano tended to at worst hang with Deneb if not show modest gains. It wouldn't be much of stretch to believe Llano would have seen similar gains when paired an L3 as well. Some more tweaks here or there and the eventual shift to 28nm would have kept the ship afloat until Zen came around. Sure, these chips would have never touched i7s, but neither did Bulldozer. Bulldozer didn't really even payoff from a tech side either, as Zen seems to have more in common with the K7/8/10 lineage than it does Zen.
 

dark zero

Platinum Member
Jun 2, 2015
2,542
100
91
Kill me, but Phenom III wouls still be competitive.... I mean... AMD won't be on Nehalem levels, but on Ivy Bridge ones... and people still uses Ivy.
 

itsmydamnation

Platinum Member
Feb 6, 2011
2,153
1,674
136
STARS is a dead end, short pipeline, limited oooE window, poor unit utilization. What people mean to say is take bulldozer chop off one side of the CMT and add an extra alu.

And all of a sudden that looks alot like Zen..........................
 

ShintaiDK

Lifer
Apr 22, 2012
20,395
128
106
Is's another thread but it seems relevant:

http://forums.anandtech.com/showthread.php?t=2469531

These results could easily be the same exact scores for the incoming Zen, at stock ~3GHz, so even assuming a strict ~4GHz wall for overclocks the chip might be really good in games and single threaded tasks.

Yet... I'm comparing it to 32nm Sandy Bridge "dinoasurs" here, the only advantage a 2016-17 chip would have is better motherboard/features and lower power?

So what would you guys say of Zen if it performed exactly like this?
There is a caverat. The SB in question got 20MB cache. Try reduce it to say 8MB and remove the quadchannel. Quite different performance.
 

prtskg

Senior member
Oct 26, 2015
249
83
101
Question: is it possible that AMD sends ES with different clocks?
I saw that report from bitsandchips about Zen ES having 3GHz but we're supposed to get Summit Ridge ES next week and the info AMD sent us last month suggests it's a lower clock.
It was April fool article. And your info is right. The ES clock is low.
 
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The Stilt

Golden Member
Dec 5, 2015
1,709
3,057
106
Personally I don't believe that AMD has sent Zen silicon to anywhere yet. The motherboard manufacturers do need AM4 APUs / CPUs in order to make their AM4 boards, but Bristol Ridge (Carrizo) chips can be used for that purpose.

The clocks on the alleged Zen "A0" part don't tell much really, even if they were true. Nowdays the manufacturers only make new, major die revisions if they absolutely have to (in order to fix errata, which cannot be fixed thru µcode). Things were different back in the day, when both AMD and Intel released steppings to improve the characteristics of the design (power consumption and scaling).

Usually the prototype chips have higher than usual safety margins (for obvious reasons), so the initial silicon revisions can clock just as high as the final ones.

Recently AMD has done very few major die revisions between the initial tape out and the release:

Orochi:

OR-A0 = 3.6GHz (initial)
OR-B0 = 4.1GHz
OR-B2F = 4.3GHz (release, +19.4%)

Trinity:

TN-A0 = 4.1GHz (initial)
TN-A1 = 4.2GHz (release)

Carrizo:

CZ-A0 = 3.4GHz (initial)
CZ-A1 = 3.4GHz (release)

Generation 1 Bulldozer was an exception, since it required four major steppings and several minor revisions before it was ready for release (still had major errata in it).

For example, Stoney Ridge launched with it's initial die revision (A0).
 

NTMBK

Diamond Member
Nov 14, 2011
8,905
1,980
136
I've always said that a Llano based Phenom III would have been more palatable than the Bulldozer experiment. Take Llano, lop off the iGPU and slap on an L3 alongside 2/4 more cores and you've got a pretty competitive chip at that point in time. Even without the L3, Llano tended to at worst hang with Deneb if not show modest gains. It wouldn't be much of stretch to believe Llano would have seen similar gains when paired an L3 as well. Some more tweaks here or there and the eventual shift to 28nm would have kept the ship afloat until Zen came around. Sure, these chips would have never touched i7s, but neither did Bulldozer. Bulldozer didn't really even payoff from a tech side either, as Zen seems to have more in common with the K7/8/10 lineage than it does Zen.
Compare Llano and Trinity, and Trinity gives it a good kicking in 1-2 thread performance, while not being as fast at 3-4 thread performance.
 

itsmydamnation

Platinum Member
Feb 6, 2011
2,153
1,674
136
There is a caverat. The SB in question got 20MB cache. Try reduce it to say 8MB and remove the quadchannel. Quite different performance.
except its 8mb per compute unit, so 16mb L3 in total for a 8 core chip. You will also have DDR4 vs DDR3 so quad channel doesn't off that much of a benefit. These fundamental mistakes aren't looking good for when you finally grace us with your wisdom and give us a detailed analysis of all the architectural mistakes AMD have made with Zen......................

Personally I don't believe that AMD has sent Zen silicon to anywhere yet.
Thevenin has been exceptionally trust worthy and generally critical of SR EX etc, he is hardly an AMD pet. He works for a OEM ( has never said which one) and says they have them.
 
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ShintaiDK

Lifer
Apr 22, 2012
20,395
128
106
except its 8mb per compute unit, so 16mb L3 in total for a 8 core chip. You will also have DDR4 vs DDR3 so quad channel doesn't off that much of a benefit. These fundamental mistakes aren't looking good for when you finally grace us with your wisdom and give us a detailed analysis of all the architectural mistakes AMD have made with Zen......................
Its really going to be hard for you if Zen isn't a top chip. :)

You better hope that the informed sources are wrong. Because its looking quite bad for Zen at the moment.
 

itsmydamnation

Platinum Member
Feb 6, 2011
2,153
1,674
136
Its really going to be hard for you if Zen isn't a top chip. :)
I wont care, i'll just do what i have done with bulldozer try and learn where the failings are.

Your the one who feels the need to push an agenda, im just asking you to backup it up with a shred of anytihng.

You better hope that the informed sources are wrong. Because its looking quite bad for Zen at the moment.
by informed sources you mean voices in your head right. There has been what i would call one credible posting around Zen and only a special flower like you could take it negatively........
 

Glo.

Diamond Member
Apr 25, 2015
4,589
3,190
136
Again, bits & chips ;)

http://www.bitsandchips.it/52-english-news/6815-speculations-about-zen-after-our-april-s-fool

They were right before on many occasions, but forum users will always neglect that. There is much more reason to believe in words of Fottemberg about this. You have to digest which is info he provides and which is his speculation(Fabbing process).

And yes, If Zen would not be delivered to clients, Thevenin would not provide word about the CPU itself, or even about Polaris, which he did.
 
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May 11, 2008
18,310
829
126
Personally I don't believe that AMD has sent Zen silicon to anywhere yet. The motherboard manufacturers do need AM4 APUs / CPUs in order to make their AM4 boards, but Bristol Ridge (Carrizo) chips can be used for that purpose.

The clocks on the alleged Zen "A0" part don't tell much really, even if they were true. Nowdays the manufacturers only make new, major die revisions if they absolutely have to (in order to fix errata, which cannot be fixed thru µcode). Things were different back in the day, when both AMD and Intel released steppings to improve the characteristics of the design (power consumption and scaling).

Usually the prototype chips have higher than usual safety margins (for obvious reasons), so the initial silicon revisions can clock just as high as the final ones.

Recently AMD has done very few major die revisions between the initial tape out and the release:

Orochi:

OR-A0 = 3.6GHz (initial)
OR-B0 = 4.1GHz
OR-B2F = 4.3GHz (release, +19.4%)

Trinity:

TN-A0 = 4.1GHz (initial)
TN-A1 = 4.2GHz (release)

Carrizo:

CZ-A0 = 3.4GHz (initial)
CZ-A1 = 3.4GHz (release)

Generation 1 Bulldozer was an exception, since it required four major steppings and several minor revisions before it was ready for release (still had major errata in it).

For example, Stoney Ridge launched with it's initial die revision (A0).
I get the following thoughts about this :
  • This means they double checked everything before the first masks were send away.
  • They have better test software.
  • Zen is performing very well.
  • Redundancy through micro code has increased.
  • And the worst case scenario i do hope will not happen for AMD, Zen will have some weird error in the near future that hopefully will be able to be fixed by a bios update but will remove a lot the of the power efficiency.
    But i do not buy that. AMD is executing very well when it comes to products.
    It is just that they need a marketing division that can be as cold-hearted and mean as they are good. AMD always comes up with good ideas to tackle performance issues years before the competition does. But they have no marketing power to enforce the benefits.
 
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grimpr

Golden Member
Aug 21, 2007
1,098
7
81
I wont care, i'll just do what i have done with bulldozer try and learn where the failings are.

Your the one who feels the need to push an agenda, im just asking you to backup it up with a shred of anytihng.



by informed sources you mean voices in your head right. There has been what i would call one credible posting around Zen and only a special flower like you could take it negatively........
You're wasting your time with this one, just ignore him completely he's not worthy of anything valuable, he became an expert intel nvidia troll in a shining knight armor, he derails amd threads constantly, he provokes at a daily basis, just look at his signature he claims that Anandtech forums is an AMD echo chamber like AMDZone. I'm gonna fill a report on this little buddy and maybe you should too.

insulting other members is not allowed
Markfw900
 
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