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New Zen microarchitecture details

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Vesku

Diamond Member
Aug 25, 2005
3,745
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With AMD confidently stating +40% vs Vishera while using "up to" for Excavator comparison, I'm expecting roughly Ivy Bridge IPC (a few programs benefiting more) with better power efficiency.
 
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sirmo

Golden Member
Oct 10, 2011
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For 90+ efficiency with varying loads you need multi-tapped inductors, and a complicated switcher to utilize the different taps for different loads... Hopefully hybrid planar inductor+mosfet VRMs will solve this problem in the future, as they can have integrated multiplexing switchers (one piece of silicon for switchers, synchronous rectification and driver IC) coupled to multiple taps on the inductor and multiplexed in real time, in step with the amount of load, all in one package (presumably all encased in sintered ferrite).

Right now using discrete components would be excessive, too much package overhead, taking up too much board real estate.
Yup, and how many board manufacturers would really go through all that trouble.. It's not like the consumer would know to pay more money for it anyways.
 

DrMrLordX

Lifer
Apr 27, 2000
16,627
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While completely true, what does releasing Radeon RX 480 at 199$ make them? :sneaky:
A midrange product launched as a result of their attempt to produce "small" dice on 14nm lpp before trying to produce the "large" high-end product (Vega).

Personally I understood the "not going to be a bargain brand anymore" statement that they won't have those <70$ APUs, which nobody really wants even for free available in retail anymore (after Zen happens).
That's part of it, but they also don't want to have to slash prices on their flagship CPU because it gets spanked so hard by Intel that nobody will buy it at its initial MSRP. Such as the 9590.

They don't want another 9590 or 9370. Demand for those chips is so depressed that you can get a 9590 for $220 and a 9370 for $184:

http://pcpartpicker.com/products/cpu/#s=23&sort=d7&page=1

Hardware.fr measured 117.6W as VRIN power from EPS12V during Prime95 on i7-6950X :sneaky: When VRM (~85%) and FIVR (~80%) losses are accounted for, that's around 80W.
. . . and that is a 10c chip that would annihilate a hypothetical 8c/16t IVB-E (or a Summit Ridge with the same IPC as the IVB-E). With that kind of power draw, 95W ain't lookin so good in comparison. Yeah the price tag is absurd, but again . . . flagship boutique product. Xeons - which compete in the server space - won't be like that.

you cant even remotely say things like this with any confidence
Why not? Intel has been beating Piledriver in throughput since at least HSW-E, if not IVB-E. Not just IPC, but total throughput. So why do I want Piledriver-based solutions in my shop if all I need is the most throughput within a given power envelope?

because if throughput was the key metric organisations wanted then server market share would have at least stabilized with bulldozers release
I'm gonna have to disagree with that.

You realize that if you have high ILP (aka throughput) then SMT provides very little in the way of performance benefit because your alreadly bottle necked in the core else where.
If the pipeline is stuffed then yes, that happens. Not that that's necessarily a bad thing.

what in almost every case is running on the bear metal? KVM/ESX/hyperV. These days the only x86 stuff you see that isn't running on a hypervisor is big DB.
That's about what I would expect, yes. Construction cores do pretty well running VMs if you can stand the heat/power usage.

This is because the hypervisor has a NUMA aware scheduler, so if you have a VM that is running a throughput workload and maxing a core ( or several) it will move workloads around accordingly to deliver the best realtime performance it can to all VM's. So two VM's that aren't doing much end up sharing a core at that point.
Yes! This is just what I was thinking when I made my argument. Total throughput becomes important here because the hypervisor will do a reasonably good job at assigning VMs to threads so that you get the most out of the available resources. It's not like 8c/16t 8 strong + 8 weak will do better here than 8m/16th 16 medium if throughput is identical, since it can move VMs around however it wishes until the CPU is doing the most possible work it can do. Intel's solutions provide more IPC *and* throughput than AMD's while achieving better perf/watt which is why they are used in these machines.

No it doesn't, it all depends how you count it. a XV module has 2xFMA units, Zen has 2xFMA a core.
Uh . . . XV modules have 2x128-bit FMACs. I thought Zen cores have four? It was rumoured that they'd be 2x256bit FMACs but they aren't, they're all 128-bit. That'll cause its own trouble down the road, but I digress.
 

sirmo

Golden Member
Oct 10, 2011
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With AMD confidently stating +40% vs Vishera while using "up to" for Excavator comparison, I'm expecting roughly Ivy Bridge IPC (a few programs benefiting more) with better power efficiency.
This is my gut feeling on it as well. I do think the power efficiency is key, and I think AMD might have something up their sleeve there.
 
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Doom2pro

Senior member
Apr 2, 2016
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This is my gut feeling on it as well. I do think the power efficiency is key, and I think AMD might have something up their slave there.
I would hope so too... After AMD having quite a few recent underwhelming CPU Arch releases, it would be pretty good for them to hide some extra performance to blow the socks off the naysayers when Zen is finally benchmarked.
 

itsmydamnation

Platinum Member
Feb 6, 2011
2,153
1,673
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Uh . . . XV modules have 2x128-bit FMACs. I thought Zen cores have four? It was rumoured that they'd be 2x256bit FMACs but they aren't, they're all 128-bit. That'll cause its own trouble down the road, but I digress.
Nope it has 4 pipes, broadly speaking two with FADD and two with FMUL. each pair FADD and FMUL have an internal interconnect ( i assume because its needs to be wider then 128bits) between them and can be used together for FMA.
 

KTE

Senior member
May 26, 2016
478
130
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Maybe it's finally time for something like ARMs Big.LITTLE concept on DT...

Sent from HTC 10
 

DrMrLordX

Lifer
Apr 27, 2000
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Nope it has 4 pipes, broadly speaking two with FADD and two with FMUL. each pair FADD and FMUL have an internal interconnect ( i assume because its needs to be wider then 128bits) between them and can be used together for FMA.
Hmm guess I was mistaken on that point. I guess I could see it not outperforming XV by all that much on a core vs. module basis then, which is a bit disappointing.
 

The Stilt

Golden Member
Dec 5, 2015
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And it's not compatible either with Zeppelin or Raven Ridge o_O
4+2 phase VRM made with D-Pak mosfets D:. Probably barely sufficient for 65W Bristol Ridge parts (due weak 2 phase VDDSoC plane, i.e GPU power).
 
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DrMrLordX

Lifer
Apr 27, 2000
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What seems to be happening is that early AM4 is going exclusively to system OEMs. Mobo OEMs apparently don't want to launch Summit Ridge-capable boards right now . . . or the specs haven't been set in stone enough for them to get product like that on the market.

But yeah I'll pass on 4+2 phase VRM layouts. My A88x-Pro is built better than that.
 

Doom2pro

Senior member
Apr 2, 2016
587
619
106
And it's not compatible either with Zeppelin or Raven Ridge o_O
4+2 phase VRM made with D-Pak mosfets D:. Probably barely sufficient for 65W Bristol Ridge parts (due weak 2 phase VDDSoC plane, i.e GPU power).
That doesn't surprise me... That motherboard will be Bristol Ridge and later versions of low end/Mainstream Zen CPUs... Btw, 125W boards exist for AM3+ that are 4+2 phase... GA-78LMT USB3 for example....

I could see this BARELY supporting a 95W HEDT Zen, even with the strict voltage requirements.
 
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The Stilt

Golden Member
Dec 5, 2015
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Btw, 125W boards exist for AM3+ that are 4+2 phase... GA-78LMT USB3 for example....
And you know how "well" they work? :sneaky:
Even most of the crappier AM3+ boards nowdays use more modern fets (higher efficiency) than the HP does.
 

Doom2pro

Senior member
Apr 2, 2016
587
619
106
And you know how "well" they work? :sneaky:
Even most of the crappier AM3+ boards nowdays use more modern fets (higher efficiency) than the HP does.
And what makes you think OEM's wont use modern low RDS(on) FETs for their AM4 boards? Especially since apparently AMD is requesting the lowest transient tolerances for AM4... Ever browse around Digikey or Mouser? Even the ducks guts FETs are pretty cheap these days...
 
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The Stilt

Golden Member
Dec 5, 2015
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And what makes you think OEM's wont use modern low RDS(on) FETs for their AM4 boards? Especially since apparently AMD is requesting the lowest transient tolerances for AM4... Ever browse around Digikey or Mouser? Even the ducks guts FETs are pretty cheap these days...
The pictured HP motherboard did use D-Paks with potted inductors :sneaky:
 

The Stilt

Golden Member
Dec 5, 2015
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They look like SO-8 to me... Seeing four pins on both sides.
The fet housing seems to be too raised for a SO-8. But anyway, the point was that the unified socket has significant potential of back firing (actual compatibility between the different designs) and the first ISV design being such garbage already shows that nothing has changed since AM3+ ERA. The manufacturers keep stretching the penny no matter what the consequences are.
 

Doom2pro

Senior member
Apr 2, 2016
587
619
106
The fet housing seems to be too raised for a SO-8. But anyway, the point was that the unified socket has significant potential of back firing (actual compatibility between the different designs) and the first ISV design being such garbage already shows that nothing has changed since AM3+ ERA. The manufacturers keep stretching the penny no matter what the consequences are.

I strongly disagree, you can clearly see four contact pads on both sides on several of the FETs... They look low profile, I don't see any raised housing.

If they were D-PAKs you would expect to see three pads on one side and a large thermal pad on the other side, it would clearly be asymmetrical. That isn't what we see here... Looks mirror imaged, four contacts... Just as you would expect with SO-8.
 
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Abwx

Diamond Member
Apr 2, 2011
9,117
902
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I strongly disagree, you can clearly see four contact pads on both sides on several of the FETs... They look low profile, I don't see any raised housing.

If they were D-PAKs you would expect to see three pads on one side and a large thermal pad on the other side, it would clearly be asymmetrical. That isn't what we see here... Looks mirror imaged, four contacts... Just as you would expect with SO-8.
There s clearly 12 SO-8 packages....
 

Doom2pro

Senior member
Apr 2, 2016
587
619
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There s clearly 12 SO-8 packages....
I know right? :rolleyes: More correctly, 12 on one side, 6 above near the other two inductors.

First thing I thought when I seen it was it reminds me of EVGA's GTX 570 VRM stage, three SO-8 FETs, two in parallel for Synchronous rectification, one for switching...
 

JDG1980

Golden Member
Jul 18, 2013
1,663
569
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And it's not compatible either with Zeppelin or Raven Ridge o_O
4+2 phase VRM made with D-Pak mosfets D:. Probably barely sufficient for 65W Bristol Ridge parts (due weak 2 phase VDDSoC plane, i.e GPU power).
Perhaps the reason why AMD didn't launch desktop Bristol Ridge for DIYers is that they didn't want this kind of crap to be released. If they hold off until Zen comes out, then vendors will have to make motherboards at least good enough to support the top stock TDP at a minimum.
 

deasd

Senior member
Dec 31, 2013
201
15
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Good clocks for A12-9800. I wonder if there's an A12-9850K model which is around 4Ghz.
 

Abwx

Diamond Member
Apr 2, 2011
9,117
902
126
I know right? :rolleyes: More correctly, 12 on one side, 6 above near the other two inductors.

First thing I thought when I seen it was it reminds me of EVGA's GTX 570 VRM stage, three SO-8 FETs, two in parallel for Synchronous rectification, one for switching...
That s right, the serie of 6 is likely for the IGP power plane..

Dont know for the GTX but D-Pack have only three connectors on one side and a metalic part on the other side for soldering, wich is not the case here..
 

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