New Zen microarchitecture details

[jpiniero]

From a practical standpoint though SB IPC would be good enough to be GPU limited in most games though assuming the clocks are not terrible. Look at where the 6 Core SB-E lands in most games that are really well threaded - maybe not at the top but very close.

 

[DrMrLordX]

then your not understanding the design very well. i'll explain when i get around to addressing your reply to my last post 🙂

Okay . . .

Hell, an 8c/16t Sandybridge-level CPU with decent clocks would be a pretty damn fine processor.

Why? Intel has had better stuff than that on the market since at least the 5960X. The only thing it would have going for it is the 95w TDP.

It's better than Vishera but it's not better than what AMD could have come up with had they just kept iterating on Construction cores.

 

[nenforcer]

Okay . . .

Why? Intel has had better stuff than that on the market since at least the 5960X. The only thing it would have going for it is the 95w TDP.

It's better than Vishera but it's not better than what AMD could have come up with had they just kept iterating on Construction cores.

This is a drastically different architecture when compared to the Construction cores - we'll really have to wait for individual benchmarks on both the Integer and Floating Point units to know for sure.

 

[IntelUser2000]

Yeah, I read that wrong lol. Isn't SMT performance going to be the same for Intel as AMD? I mean, it's just using leftover resources on that core, right? So, if a hardware core is at 70% utilization, SMT can only provide 30% on that logical OS core (considering all things equal and evenly split).

Not that simple.

Pentium 4's SMT was at a higher level same as Skylake's SMT. However, the details made all the difference. Pentium 4's SMT was effective enough by Northwood C generation, but there still were fair bit of cases where it was good turning it off. With Skylake that's almost nonexistent.

That's why Stilt is saying that Intel has 12 years of real-world experience. Delays and missteps happen likely because what you planned(or theorized) don't pan out in reality.

IBM's Power 8 chips have fantastic clock speeds and multi-threading performance, but per clock Intel chips still have the lead by a decent margin. And consumer workloads requirements are very different from server. A certain subsection of people would cry out for 2% degradation in single thread if Intel decided to use 4-way SMT to improve multi-threading performance by 10%.

CPU workloads can't be characterized by improving a single unit. Intel's overall architecture is well-balanced which is why they fare well regardless of whether it's FP or Integer.

Of course, there's no doubt AMD will be far closer to Intel than ever. But will have closed the gap because they are more competent than Intel or because its just diminishing returns at that point?

 

[KTE]

Why would one have separate base and 8C turbo frequencies? :sneaky:

So what's your expectation from what you know so far?


Even if Zen came with an average +65% performance gain over Excavator (a huge unknown), it would need matching Price, Power and Frequencies to what Intel offers by Q1 2017 to be competitive, recommendable and sell. It would also need to have mass availability, mainly through OEMs, by Q4 2016.

The odds are highly stacked.

Sent from my HTC 10 using Tapatalk

 

[The Stilt]

The base frequency will be limited by the TDP (that's the whole point of having Turbo), but how low will it end up being is matter of the characteristics of 14nm LPP process. 14nm LPP is extremely power efficient at it's optimal operating window, but the question is at what rate does the efficiency deteriorate as the frequency stretches out of the window.

I would expect the base frequency to be 2.8GHz (±200MHz) for the fastest Zeppelin SKU (8C/16T, 95W).

AMD has been so far behind in process technology for years that they have had to develop extremely efficient power management in order to compensate the process deficiency the best they can. I personally rank the power management on Carrizo and newer designs much higher than Intel's, in terms of efficiency and features. Zen should be using pretty much identical PM as Excavator (CZ/BR/ST), with some generational improvements of course (directly related to frequency). I expect the maximum boost frequency to settle in the 3.6GHz range (±100MHz) and that the maximum boost is available to two cores (with or without SMT enabled) simultaneously. Due the way the PM works in Excavator based designs and the changes AMD made to it in Zen, I expect the average frequency to vary quite a lot depending on the workload and the number of utilized cores / CCXs.

So far I think I've said anything between 2.6GHz - 3.2GHz as the base and anything between 3.2GHz - 3.8GHz for the maximum boost.

However I stick with 2.8GHz (±200MHz) for the base and 3600MHz (±100MHz) for the maximum boost. I also do expect that AMD will release the Zeppelin AM4 SKUs clocked "balls to the wall" in terms of the default boost frequency. The extremely strict VRM requirements and the new extremely precise frequency control method point in this way.

Higher TDP would naturally allow higher base frequencies but not boost frequencies, which I expected to be limited by the manufacturing process.

With "not able to hit higher than x" I mean the frequencies AMD can actually ship the parts at (as a normal, consumer grade SKU), and not the frequencies some halfwit can hit while supplying 1.6V to the CPU, making it consume 310W.

 

[el etro]

How the processor will achieve different turbo speeds for 1C and for 8C? Aggressive power management of couse!

 

[The Stilt]

How the processor will achieve different turbo speeds for 1C and for 8C? Aggressive power management of couse!

It is pretty silly to have 8C "turbo frequency". Usually it is called as base :sneaky:

 

[KTE]

The base frequency will be limited by the TDP (that's the whole point of having Turbo), but how low will it end up being is matter of the characteristics of 14nm LPP process. 14nm LPP is extremely power efficient at it's optimal operating window, but the question is at what rate does the efficiency deteriorate as the frequency stretches out of the window.

I would expect the base frequency to be 2.8GHz (±200MHz) for the fastest Zeppelin SKU (8C/16T, 95W).

AMD has been so far behind in process technology for years that they have had to develop extremely efficient power management in order to compensate the process deficiency the best they can. I personally rank the power management on Carrizo and newer designs much higher than Intel's, in terms of efficiency and features. Zen should be using pretty much identical PM as Excavator (CZ/BR/ST), with some generational improvements of course (directly related to frequency). I expect the maximum boost frequency to settle in the 3.6GHz range (±100MHz) and that the maximum boost is available to two cores (with or without SMT enabled) simultaneously. Due the way the PM works in Excavator based designs and the changes AMD made to it in Zen, I expect the average frequency to vary quite a lot depending on the workload and the number of utilized cores / CCXs.

So far I think I've said anything between 2.6GHz - 3.2GHz as the base and anything between 3.2GHz - 3.8GHz for the maximum boost.

However I stick with 2.8GHz (±200MHz) for the base and 3600MHz (±100MHz) for the maximum boost. I also do expect that AMD will release the Zeppelin AM4 SKUs clocked "balls to the wall" in terms of the default boost frequency. The extremely strict VRM requirements and the new extremely precise frequency control method point in this way.

Higher TDP would naturally allow higher base frequencies but not boost frequencies, which I expected to be limited by the manufacturing process.

With "not able to hit higher than x" I mean the frequencies AMD can actually ship the parts at (as a normal, consumer grade SKU), and not the frequencies some halfwit can hit while supplying 1.6V to the CPU, making it consume 310W.

And IPC wise?

Jumping to TSMCs 10nm process might be worthwhile for AMD.


Sent from HTC 10

 

[JDG1980]

Why? Intel has had better stuff than that on the market since at least the 5960X. The only thing it would have going for it is the 95w TDP.

The 5960X is a $1000 CPU with a 140W TDP. If AMD can offer 70%-80% of the MT performance and 80%-90% of the ST performance, in a 95W package at a $299-$399 price point, that's going to get a lot of takers.

For reference, the going rate on eBay for a used Sandy Bridge E5-2687W CPU (8C/16T, 3.1 GHz base, 3.8 GHz turbo) is about $350. That has a TDP of 150W and requires an expensive LGA 2011 motherboard- not to mention that it comes with no warranty or support of any kind. You don't think that kind of performance at 95W on a fully supported modern platform would sell decently at the right price?

It's better than Vishera but it's not better than what AMD could have come up with had they just kept iterating on Construction cores.

Hard to prove a hypothetical, but all the signs point to the construction cores having fundamental, unfixable structural problems. Everything we've seen indicates they were simply inferior designs. Even after four iterations (BD->PD->SR->XV), IPC is still hardly up to par with Conroe and Thuban, and well behind Nehalem.

 

[JDG1980]

The base frequency will be limited by the TDP (that's the whole point of having Turbo), but how low will it end up being is matter of the characteristics of 14nm LPP process. 14nm LPP is extremely power efficient at it's optimal operating window, but the question is at what rate does the efficiency deteriorate as the frequency stretches out of the window.

Do we know for a fact that Summit Ridge will in fact be manufactured on GloFo 14LPP? AMD has generally been careful to mention only "FinFET" in its marketing materials, not any specific process.

I agree it's most likely they will do that, but if the GloFo process turns out to be completely unsuitable for high frequency CPUs, then there is still the possibility they could go with TSMC 16FF+ for the flagship Zen products, and fill their WSA quota with GPUs and console APUs.

I can't find the exact quote, but I remember an interview with Tom's Hardware where Lisa Su said that Zen was a "bet-the-company" product. I don't think they are going to let an unsuitable process node drag that down. And I don't think they will release the flagship Summit Ridge product with a base clock below 3.0 GHz at a minimum.

 

[LTC8K6]

It is pretty silly to have 8C "turbo frequency". Usually it is called as base :sneaky:

IIRC, some Intel chips have an all core turbo frequency that is above the base clock. My 1231 V3 at stock seems to have a 3.4 base, 3.6 all core turbo, 3.8 single core turbo, for example.

4790K at stock seems to be 4.0 base, 4.2 turbo on all cores, and 4.4 turbo on one core.

 

[jpiniero]

Do we know for a fact that Summit Ridge will in fact be manufactured on GloFo 14LPP? AMD has generally been careful to mention only "FinFET" in its marketing materials, not any specific process.

It's possible but AFAIK it was in relation to the GPUs and not necessarily any CPU or APU.

 

[sirmo]

Do we know for a fact that Summit Ridge will in fact be manufactured on GloFo 14LPP? AMD has generally been careful to mention only "FinFET" in its marketing materials, not any specific process.

I agree it's most likely they will do that, but if the GloFo process turns out to be completely unsuitable for high frequency CPUs, then there is still the possibility they could go with TSMC 16FF+ for the flagship Zen products, and fill their WSA quota with GPUs and console APUs.

I can't find the exact quote, but I remember an interview with Tom's Hardware where Lisa Su said that Zen was a "bet-the-company" product. I don't think they are going to let an unsuitable process node drag that down. And I don't think they will release the flagship Summit Ridge product with a base clock below 3.0 GHz at a minimum.

They probably have a pretty good understanding of the Samsung 14nm LPP process, based on specs. They don't only have a WSA with Global Foundries for it, they also have one with Samsung directly, so they can fab Zen at GloFo or Samsung. I think the reason they are moving all their designs to 14nm LPP is for their semi custom business, this allows them the ability to use the same exact design in both fabs. The semi custom customer configures a SoC from AMD's IP blocks (including the Zen cores) and they can fab it in either fab.

Using 16nm would require them to have to design all their components (GPUs, Zen core, uncore...) for different processes which is double the work. They don't have Apple money to waste and do that.

 

[ShintaiDK]

They don't only have a WSA with Global Foundries for it, they also have one with Samsung directly, so they can fab Zen at GloFo or Samsung.

AMD doesn't have a WSA with Samsung. And thank god for that, its bad enough they got one with Glofo.

There is nothing pointing to "dual sourcing" either.

 

[coffeemonster]

Even after four iterations (BD->PD->SR->XV), IPC is still hardly up to par with Conroe and Thuban, and well behind Nehalem.

what are you basing that on? that is wildly contradictory to what has already been shown in the carizzo/bristol ridge threads.

 

[The Stilt]

Do we know for a fact that Summit Ridge will in fact be manufactured on GloFo 14LPP? AMD has generally been careful to mention only "FinFET" in its marketing materials, not any specific process.

I agree it's most likely they will do that, but if the GloFo process turns out to be completely unsuitable for high frequency CPUs, then there is still the possibility they could go with TSMC 16FF+ for the flagship Zen products, and fill their WSA quota with GPUs and console APUs.

I can't find the exact quote, but I remember an interview with Tom's Hardware where Lisa Su said that Zen was a "bet-the-company" product. I don't think they are going to let an unsuitable process node drag that down. And I don't think they will release the flagship Summit Ridge product with a base clock below 3.0 GHz at a minimum.

Some of the older slides say 14nm FinFet. Since only Intel and Samsung / GlobalFoundries have 14nm process available... I don't know if has been announced in public, but the process is GlobalFoundries 14nm LPP to be specific. Made in Fab 8 NY.

Sure, AMD could definitely port Zeppelin to 16nm FF+ if necessary...
However that would add anything between 6-12 months of additional delay, and cost millions.

 

[frozentundra123456]

Do we know for a fact that Summit Ridge will in fact be manufactured on GloFo 14LPP? AMD has generally been careful to mention only "FinFET" in its marketing materials, not any specific process.

I agree it's most likely they will do that, but if the GloFo process turns out to be completely unsuitable for high frequency CPUs, then there is still the possibility they could go with TSMC 16FF+ for the flagship Zen products, and fill their WSA quota with GPUs and console APUs.

I can't find the exact quote, but I remember an interview with Tom's Hardware where Lisa Su said that Zen was a "bet-the-company" product. I don't think they are going to let an unsuitable process node drag that down. And I don't think they will release the flagship Summit Ridge product with a base clock below 3.0 GHz at a minimum.

You wouldnt have thought they would let a flawed architecture drag down Bulldozer, but they did. By your reasoning, no company would ever release a bad product.

 

[sirmo]

AMD doesn't have a WSA with Samsung. And thank god for that, its bad enough they got one with Glofo.

There is nothing pointing to "dual sourcing" either.

http://forums.anandtech.com/showthread.php?t=2458413

AMD has a long standing WSA with GloFo till 2019. They also have a WSA with TSMC for 28nm console and GPU chips. And that story I linked points to a WSA with Samsung.

 

[ShintaiDK]

http://forums.anandtech.com/showthread.php?t=2458413

AMD has a long standing WSA with GloFo till 2019. They also have a WSA with TSMC for 28nm console and GPU chips. And that story I linked points to a WSA with Samsung.

The WSA with GloFo runs till March 2. 2024.
http://ir.amd.com/mobile.view?c=740...ERVNDPVNFQ1RJT05fUEFHRSZleHA9JnN1YnNpZD01Nw==

Nothing you linked shows a WSA with anyone else.

 

[el etro]

It is pretty silly to have 8C "turbo frequency". Usually it is called as base :sneaky:

No. Usually is called "How far it can go based on power and temperature limits". Like Nvidia and AMD GPUs does.

 

[sirmo]

The WSA with GloFo runs till March 2. 2024.
http://ir.amd.com/mobile.view?c=740...ERVNDPVNFQ1RJT05fUEFHRSZleHA9JnN1YnNpZD01Nw==

Nothing you linked shows a WSA with anyone else.

Correction, you're right it is in 2024. WSA is just a generic term for a contract with a fab. I just linked you to the story that says they have it with Samsung? Are you disputing the validity of the source or what? I am confused.

 

[KTE]

IIRC, some Intel chips have an all core turbo frequency that is above the base clock. My 1231 V3 at stock seems to have a 3.4 base, 3.6 all core turbo, 3.8 single core turbo, for example.

4790K at stock seems to be 4.0 base, 4.2 turbo on all cores, and 4.4 turbo on one core.

It occurs only if and when the Icc limits and W are configurable (like in the BIOS), overrideable in software (MSRs) or when the full CPU is running below the set power limits. You need a thermal budget for this (very cool running).

Keep in mind that AMD typically places a 10-15% Vdd buffer to deal with transients and process variations, keep the Vdd higher than necessary for better yields, and they tend to keep higher Vt to minimize subthreshold leakage in the Ioff state... which leads to lower possible switch frequencies.

Leakage and operating junction temperatures are directly linked to power density and hotspots (more so in smaller nodes), and that all to resistance and power draw (especially static).

Also a microprocessor arch and a process is designed and optimized for a set frequency and power range. Above and below which, they generally become very inefficient/unstable.

Sent from HTC 10

 

[DrMrLordX]

This is a drastically different architecture when compared to the Construction cores - we'll really have to wait for individual benchmarks on both the Integer and Floating Point units to know for sure.

While this is true, it does not brush away the fact that Summit Ridge can be compared to XV on a core-by-core/module-by-module basis in terms of raw performance (notably throughput).

The 5960X is a $1000 CPU

It's current pricing is due to its position as last generation's boutique flagship product. Do not think Intel must sell it at that price. There are any number of Xeons providing similar performance at lower prices, albeit without the unlocked multi.

Bottom line is that Intel has had multicore Haswell-E parts since Q3 2014 with 8c and more. Yet AMD is chasing Sandy Bridge?!? The TDP is nice, but Intel's relative performance per watt has improved with Broadwell-E already, and Skylake-E is the next competitor in line . . .

If AMD can offer 70%-80% of the MT performance and 80%-90% of the ST performance, in a 95W package at a $299-$399 price point, that's going to get a lot of takers.

Why? Except for the "I hate Intel" crowd - and there are some people like that, even in corporate space - I don't see this happening much if at all. AMD has said that they aren't going to be the "bargain" brand anymore. $299 Summit Ridge makes them the bargain brand.

Don't get me wrong, I think $299 8c/16t anything sounds like fun . . . I just don't see them doing well in server rooms and data centers with that.

For reference, the going rate on eBay for a used Sandy Bridge E5-2687W CPU (8C/16T, 3.1 GHz base, 3.8 GHz turbo) is about $350. That has a TDP of 150W and requires an expensive LGA 2011 motherboard- not to mention that it comes with no warranty or support of any kind. You don't think that kind of performance at 95W on a fully supported modern platform would sell decently at the right price?

Those prices are inflated by numerous factors we can't even take into account here. If anything I expect prices on used SB-E, IVB-E, and HSW-E processors to take a dump if Summit Ridge is the "bargain" HEDT/Workstation CPU that people are projecting here.

Hard to prove a hypothetical

XV is here already, and has been since last year. We know what it can do, even with no L3 cache and an undersized L2. Extrapolate over multiple cores.

but all the signs point to the construction cores having fundamental, unfixable structural problems.

. . . really? If you have followed the Construction core progression from Bulldozer to Excavator, then you've seen a great deal of improvement. 8c/16t XV just based off Carrizo numbers would be pretty damn good! They could have had low power server parts in the 2.5-3 GHz range and TDPs in the 60-95W range in 2015 just on the old 28nm SPP, not to speak of what they could have achieved by now using 22nm FDSOI or 22FDX.

All the tech was there. They needed the funds and manpower to make it happen, and all that was diverted elsewhere. That elsewhere had better lead to something better than what it's obvious that they could have done by now with XV.

 

[The Stilt]

IIRC, some Intel chips have an all core turbo frequency that is above the base clock. My 1231 V3 at stock seems to have a 3.4 base, 3.6 all core turbo, 3.8 single core turbo, for example.

4790K at stock seems to be 4.0 base, 4.2 turbo on all cores, and 4.4 turbo on one core.

I would assume that on Intel base and all core turbo exists because of the same thing why Broadwell-E got "Turbo Boost Max 3.0", i.e different clocks for AVX2 and non-AVX2 workloads (difference in power draw).

Zen shouldn't have a drastic difference in power consumption between AVX2 and non-AVX2 workloads, as far as I've understood it.