Discussion Mediatek SoC thread

[DZero]

Ahem...

The maximum amount of L2 cache the Cortex A725 can be configured with is 1 MB.

Even Dimensity 9400 only has a total of 7 MB of L2 private caches across it's 8 cores.

Is 1 MB per core or per cluster? If is per core, it fits since the A725 on the big cores only uses 1 MB and on the "small ones" just 512 kb.
If is per cluster, well, time to use the L3 cache then.

 

[FlameTail]

Is 1 MB per core or per cluster? If is per core, it fits since the A725 on the big cores only uses 1 MB and on the "small ones" just 512 kb.
If is per cluster, well, time to use the L3 cache then.

ARM cores cannot be put in a cluster with shared L2.

That's why Apple/Qualcomm's CPU is special.

 

[MS_AT]

ARM cores cannot be put in a cluster with shared L2.

That's why Apple/Qualcomm's CPU is special.

Not sure about the newest ones but AMD/Xilinx is using a72s and a53s in its FPGA SoCs with shared L2 as LLC

 

[DZero]

ARM cores cannot be put in a cluster with shared L2.

That's why Apple/Qualcomm's CPU is special.

So, is per core no? If that so, that is what I mean. I should added "total" in the part, but the idea is the same mentioned previously.

 

[Nothingness]

Not sure about the newest ones but AMD/Xilinx is using a72s and a53s in its FPGA SoCs with shared L2 as LLC

Are you sure of that? The private (but coherent) L2 is mandatory IIRC.

 

[MS_AT]

Are you sure of that? The private (but coherent) L2 is mandatory IIRC.

https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/Arm-v8-Architecture hopefully the link points to the correct place. https://docs.amd.com/viewer/attachment/dqE2tE0k~iMhpEDoQwXIKg/DH_fGSDkzyH4lTKZ0NNiBg

The Cortex-A53 MPCore processor’s L2 memory system size is 1 MB. It contains the L2 cache pipeline and all logic required to maintain memory coherence between the cores of the cluster.

Anyway there are up to 4 cores in the cluster. Unless there is something that evades me, I think it is fair to say the cores in the cluster share the L2 cache.

AMD/Xilinx Versal should be similar but with A72 cores. Versal Gen2 is using A78 cores and indeed has L2 private caches and then L3.

 

[Nothingness]

https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/Arm-v8-Architecture hopefully the link points to the correct place. https://docs.amd.com/viewer/attachment/dqE2tE0k~iMhpEDoQwXIKg/DH_fGSDkzyH4lTKZ0NNiBg

Anyway there are up to 4 cores in the cluster. Unless there is something that evades me, I think it is fair to say the cores in the cluster share the L2 cache.

AMD/Xilinx Versal should be similar but with A72 cores. Versal Gen2 is using A78 cores and indeed has L2 private caches and then L3.

Sorry I wasn't clear: I was talking about A72 not A53.

 

[MS_AT]

Sorry I wasn't clear: I was talking about A72 not A53.

https://docs.amd.com/r/en-US/am011-versal-acap-trm/Features?tocId=gx43DWsCtVGZ6t6wLtyJ6A here is a link to Versal with A72, I think the block diagrams and general description are suggesting identical layout with respect to L2 as in case of Ultrascale [A53].

 

[DZero]

I want to see how efficient will be the first A725 all core processor. Maybe the champ of efficiency would be there.

 

[FlameTail]

Dimensity 8400 core configuration rumoured:

Sounds great.

The first SoC for midrange android phones with all OoO cores, and with only one core uarch too (A725)!

 

[DZero]

Now SD 7 should be all Out of Order cores too in order to not be left behind.

PS: There is a clarification. Indicates that there are 2 clusters... one with A725 and another with A720

 

[hemedans]

Now SD 7 should be all Out of Order cores too in order to not be left behind.

PS: There is a clarification. Indicates that there are 2 clusters... one with A725 and another with A720

7+ and 8s use Cortex X so perfomance wise they won't be left behind, especially if they use Phoenix-L or X925. But efficiency wise I won't be suprised if D8400 to be better than even D9400.

 

[DZero]

7+ and 8s use Cortex X so perfomance wise they won't be left behind, especially if they use Phoenix-L or X925. But efficiency wise I won't be suprised if D8400 to be better than even D9400.

D8100 all over again. Seems that my next phone will use that processor.

 

[FlameTail]

Dimensity 9400 die shot by Kurnal;

Die size = 10.81×11.68 = 126 mm²

 

[FlameTail]

Comparison of die areas of latest smartphone SoCs.

All 3 SoCs are fabbed on TSMC N3E, which it makes it an iso-node comparison.

All numbers are in mm².



• D9400, 8E dieshots from Kurnal. A18 Pro dieshot by Chipwise and annotation by High Yield.
• For Dimensity 9400, all core areas include the private L2 cache, except for the one with the asterisk. Measuring the Cortex X925 area without L2 was a pain, and I cannot vouch that the figure is accurate.

Edit: Forgot to add;

A18 Pro
P Cluster = 12.00 mm²
E cluster = 4.82 mm²

 

[FlameTail]

Pretty surprising how small the X4 core is, even with the 1 MB L2 included.

 

[FlameTail]

Chungus core. Oryon-L is also a chonker. Similar PPC.

Oryon-L is the smallest core out of all the P-cores (See above chart). Whereas Cortex X925 is the biggest (if you include the private L2). Without it Cortex X925 is still larger than Oryon-L, but smaller than A18-P.

 

[jdubs03]

Oryon-L is the smallest core out of all the P-cores (See above chart). Whereas Cortex X925 is the biggest (if you include the private L2). Without it Cortex X925 is still larger than Oryon-L, but smaller than A18-P.

I thought Oryon-L was around 2.55mm^2?

 

[FlameTail]

I thought Oryon-L was around 2.55mm^2?

That is the original Oryon core in X Elite (N4P).

8 Elite (N3E) has Oryon-L (2.1 mm²) and Oryon-M (0.85 mm²).

 

[jdubs03]

That is the original Oryon core in X Elite (N4P).

8 Elite (N3E) has Oryon-L (2.1 mm²) and Oryon-M (0.85 mm²).

Ah right, I have the image of the various recent chip offerings (from Reddit that I know you’ve seen). That has it a 2.2 mm².

 

[soresu]

Oryon-L is the smallest core out of all the P-cores (See above chart). Whereas Cortex X925 is the biggest (if you include the private L2). Without it Cortex X925 is still larger than Oryon-L, but smaller than A18-P.

Blows my mind that all the CPU manufacturers don't pool money into research for SRAM replacements.

It's such an area hog, and you know that adds up over a whole wafer.

 

[adroc_thurston]

Blows my mind that all the CPU manufacturers don't pool money into research for SRAM replacements.

Well there's SOT-MRAM but that's far away.

It's such an area hog, and you know that adds up over a whole wafer.

DRAM is an even worse problem. alas.

 

[adroc_thurston]

Comparison of die areas of latest smartphone SoCs.

All 3 SoCs are fabbed on TSMC N3E, which it makes it an iso-node comparison.

All numbers are in mm².

View attachment 111166

• D9400, 8E dieshots from Kurnal. A18 Pro dieshot by Chipwise and annotation by High Yield.
• For Dimensity 9400, all core areas include the private L2 cache, except for the one with the asterisk. Measuring the Cortex X925 area without L2 was a pain, and I cannot vouch that the figure is accurate.

Edit: Forgot to add;

A18 Pro
P Cluster = 12.00 mm²
E cluster = 4.82 mm²

oh. 3.43 on N3e with only 2M L2 is pretty chungus.

 

[soresu]

DRAM is an even worse problem. alas.

A worse problem, but not the problem of the CPU manufacturers who aren't footing that bill for their wafers (at least for those not using eDRAM anyway).

Hopefully future multilayered 3D DRAM will begin to address it.

This recent breakthrough is likely to take a long time to commercialise, but it's interesting none the less, at 5000 seconds retention it is even better than the capacitorless DRAM designs which are >400 seconds retention.

Stanford team proposes hybrid gain cell memory to boost GPU performance – Blocks and Files

A Stanford University team is researching gain cell memory, combining SRAM and DRAM features, to speed GPU-memory data access.

blocksandfiles.com

 

[FlameTail]

Kurnal's video about Dimensity 9400;

Some screenshots:

Pretty remarkable video consisting of core area comparisons, cache area comparisons, density calculations, cost calculations, etc...