Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

---------------------------------------------------------------------------------------------------------------------------------------------------


FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[maddie]

Would atomically thin oxide layers really change the overall thermal resistance that much? If so, someone needs to turn that into a house paint so you can paint yourself to a higher R value!

Lets take this reasoning to its ultimate. Seeing that all the layers are "atomically thin", then thermal resistance should be a non issue for any layout.

 

[maddie]

Since this was one of the biggest issue with BSPDN, it came up in the beginning and when asked, Intel did mention that they've solved it (but didn't share more info). If BSPDN still has such a fundamental issue, both TSMC & Intel wouldn't have bothered to adopt it in the first place.

In fact Panther Lake for laptops is coming out next year with BSPDN. So, both Intel's PowerVia and TSMC's SPR can't be that bad.

As a previous exchange stated, after being mislead so, so, many times previously, how about seeing the products before rapturously celebrating what is basically a PR proclamation.

One would think experience should be a teacher

 

[maddie]

Since this was one of the biggest issue with BSPDN, it came up in the beginning and when asked, Intel did mention that they've solved it (but didn't share more info). If BSPDN still has such a fundamental issue, both TSMC & Intel wouldn't have bothered to adopt it in the first place.

Again, did you read it.

TSMC is recommending it for HPC. I assume this is code for "best suitable for products where the added expense and complexity of advanced cooling methods can be profitably utilized"

 

[SiliconFly]

.

 

[maddie]

Lets try again. Intel is coming out with Panther Lake for laptops for next year. At this point, I think it's safe to say both Intel 18A & Panther Lake are not imaginary anymore. They're pretty much real I think regardless of the PR. If Intel's BSPDN is gonna go thermonuclear, then Panther Lake wouldn't exist at all.

And we also know TSMC's BSPDN (SPR) is supposed to be a better implementation than PowerVia. So, all evidence points to this, TSMC's Super Power Rail just can't be as bad as you say it is.

I'm not saying its bad, or that it can't be used, just that it's best as a solution for a certain class of products, not a general purpose, super duper, silver bullet, for all computing problems. That's all the info posted above stated, no incoming doomsday.

Why is AMD using older nodes for V-cache die? Great engineering is learning how to compromise well, as you can't do everything simultaneously.

 

[SiliconFly]

.

 

[maddie]

AMD almost always prefers older nodes. Their latest & greatest Zen 5 client chiplets are still on N4 when the rest of the world has moved to N3. They do it cos it's cheaper, meets their requirements, which helps them squeeze better margins from their customers.

Thus a wise compromise.

 

[SiliconFly]

.

 

[poke01]

AMD almost always prefers older nodes. Their latest & greatest Zen 5 client chiplets are still on N4 when the rest of the world has moved to N3. They do it cos it's cheaper, meets their requirements, which helps them squeeze better margins from their customers.

Nvidia is still on N4P. You don’t need the latest nodes if your architecture and IP is still good. I suspect all leading nodes will be used on AI and gaming GPUs will be on older nodes

 

[maddie]

Interesting. But this thread focuses more on Leading Edge Foundry tech. Not older tech.

Yes, but in advocating the latest, one should be wise in indicating where it is not the best choice, except for a no compromise leading edge tech solution. There are such fields, but general purpose computing is not. Otherwise, we run into fantasy speculation, which some might stray and get lost.

 

[SiliconFly]

.

 

[ajsdkflsdjfio]

Yes, but in advocating the latest, one should be wise in indicating where it is not the best choice, except for a no compromise leading edge tech solution. There are such fields, but general purpose computing is not. Otherwise, we run into fantasy speculation, which some might stray and get lost.

Leading edge nodes are completely fine for general purpose computing at least in both the recent past and in the present. Unless products like panther lake, arrow lake, various M and A series chips from apple, Tensor from google, Qualcomm snapdragon. At the time when Nvidia Lovelace was being produced TSMC n3 was still not in mass production meaning that TSMC 4N process was leading edge. Of course n-1 nodes are still viable for general purpose compute but that doesn't detract from the fact that leading edge nodes have been and continue to be widely used in general purpose compute chips.

With chiplet technology allowing for smaller more expensive dies being produced at higher yields, working together with supplementary dies and connected through base level dies usually on trailing edge nodes, even with rapidly increasing wafer prices there still likely will be a place for leading edge nodes in general purpose computing. Maybe some change in the future of computing or the market will make leading edge nodes unsuitable for GPC but at present that's just simply not the case.

On your point about TSMC SPR and Intel BSPDN being only for HPC liquid cooled applications. Firstly there are a ton of consumer level products that have cooling per area requirements similar to HPC products and are just fine on air-coolers. Also you are extrapolating liquid-cooled from TSMC making a tiny little note on recommending the node being used for "actively cooled" applications. You are then taking this extremely wild speculation and then applying it to a completely different technology from a different company using different methods of production and using it to say BSPDN is not suitable for GPC (you didn't actually say this word for word but I assume this is what you are defending/insinuating). Regardless any speculation of this manner is already your so called "fantasy speculation".

 

[maddie]

You are then taking this extremely wild speculation and then applying it to a completely different technology from a different company using different methods of production and using it to say BSPDN is not suitable for GPC (you didn't actually say this word for word but I assume this is what you are defending/insinuating). Regardless any speculation of this manner is already your so called "fantasy speculation".

I would follow the old adage about assuming, and I'll leave it at that. Thank you.

 

[QuickyDuck]

For BSPD, it's about weather the cost justify the gain. It's best for HPC that can be benefit from extra power, density despite being harder to dissipate heat. For customers of TSMC, they have choices to make. Wonder if intel has any choice.

 

[ajsdkflsdjfio]

I would follow the old adage about assuming, and I'll leave it at that. Thank you.

Even minus the BSPDN not suitable for GPC part, you did in fact claim outright that latest nodes aren't suitable for GPC despite the entire portfolio of existing products and future products designed on leading edge nodes. You seem to believe TSMC SPR is only suitable for HPC liquid cooling based on the line "actively cooled" and rudimentary analysis of increased thermal resistances, which in my books is both assumption and wild fantasy speculation.

I only included the part about BSPDN because much of this discussion about leading edge nodes and BSPD also includes intel's BSPDN implementation, and you are pretty adamant about their supposed weaknesses outside of pricing.

 

[FlameTail]

So smartphone SoCs will use N2P, not A16?

 

[adroc_thurston]

So smartphone SoCs will use N2P, not A16?

No. BSPDN just means moar heat density.

 

[LightningZ71]

There are periodic rumors of the big chip makers looking real hard at thermal bias as a means of handling these heat issues...

 

[maddie]

There are periodic rumors of the big chip makers looking real hard at thermal bias as a means of handling these heat issues...

I assume you mean vias.

Did some very, very rough calcs once and found it challenging/impossible to get enough heat pathway area to make much difference. Was looking at stacking many active circuit layers. How really feasible was it.

Too bad we don't have room temp superconductors. We could slip it between layers and shift the heat sideways, but then signal corruption by induction effects would probably kick in hard. TANSTAAFL.

 

[FlameTail]

Rumour:

Intel, AMD, Apple, Nvidia, and MediaTek tipped to use TSMC's cutting-edge 2 nm node; Qualcomm notably absent

TSMC's upcoming 2 nm node has plenty of high-profile customers such as AMD, Apple, Intel, Nvidia, MediaTek, Broadcom and Bitmain. The chips will be used in a wide array of devices, ranging from smartphones to cryptocurrency mining ASICs.

www.notebookcheck.net

Or... Intel Foundry perhaps?

Could Qualcomm be one of Intel's secret customers!?
View attachment 112259
18A (2025) is not suitable for mobile, but 18A-P (2026) is optimized for it.

Snapdragon 8 Elite Gen 3 could be made on Intel 18A-P.

According to rumours, we know Snapdragon 8 Elite Gen 2 will be on TSMC N3P. Presumably, X Elite Gen 2 will also use the same node.

8 Elite Gen 2 (2025) was supposed to be dual sourced between TSMC N3P and Samsung SF2, but Qualcomm reportedly cancelled the latter due to terrible yields of Samsung's node. So it's unlikely Qualcomm will go to Samsung for 8 Elite Gen 3 (2026).

Of course, the above Notebookcheck rumour could be wrong. And lack of evidence doesn't mean Qualcomm won't use TSMC N2. Perhaps they still haven't signed up to use it.

Qualcomm did once do an evaluation of Intel Foundry;

Qualcomm, which designs chips and outsources manufacturing, wanted to work with Intel, and assigned a team of engineers to work toward making mobile-phone chips at Intel’s factories. It was particularly interested in a cutting-edge chip-making technology that Intel hopes will be the most advanced in the world by late next year.

In early 2022, Intel’s foundry arm sent a delegation to Qualcomm’s San Diego headquarters, where they met with CEO Cristiano Amon. Then Intel missed a June performance milestone toward producing those chips commercially. It missed another in December.
Qualcomm executives concluded Intel would struggle making the kind of cellphone chips they wanted, even if it succeeded in making high-performance processors. Qualcomm told Intel it was pausing work while it waits for Intel to show progress, according to people involved in the discussions

https://www.wsj.com/articles/intel-gelsinger-nvidia-turnaround-30febac6

Qualcomm likes dual sourcing from two foundries. Historically, it was TSMC and Samsung. But with Samsung having become so uncompetitive (falling behind in node PPA as well as terrible yields), the only alternative they have left is Intel Foundry.

 

[LightningZ71]

I assume you mean vias.

Did some very, very rough calcs once and found it challenging/impossible to get enough heat pathway area to make much difference. Was looking at stacking many active circuit layers. How really feasible was it.

Too bad we don't have room temp superconductors. We could slip it between layers and shift the heat sideways, but then signal corruption by induction effects would probably kick in hard. TANSTAAFL.

Yup, meant Vias... Autocorrect got me (it just tried again ..)

I wonder if microscopic peltier junctions, thousands of them, might help?

 

[maddie]

Yup, meant Vias... Autocorrect got me (it just tried again ..)

I wonder if microscopic peltier junctions, thousands of them, might help?

To do this stuff, we need to do mathematical modelling, not language narrative, as I'm sure you know. Narrative though, is a good introduction in explaining these things to the non- technical.

Having said that, these heat densities are approaching cooking hotplate levels, eg, 70 W for a 70 mm^2 chiplet.

A few mm^2 in a chiplet dedicated to transferring this heat to the surface seems futile, unless the ∆T was very large, which means the chip interior (hot spots) would have to be much hotter than the surface temps, which is ambient at best, baring chilled cooling, and if you dedicated a large area of the die, there goes all the node density advantages.

I guess this is a bigger problem than it seems initially. If/when it's solved then we have a path to great stuff.

 

[LightningZ71]

I get that the details lie in the numbers and that the problem is very technical under the surface. In the end, the heat has to be dealt with somehow, and heat disposal is far from a new issue. Passive migration of heat from the cores will hit hard limits and require active intervention to remove it. It may even require microscopic channels moving coolant in a closed loop inside of the chips themselves. The industry long moved past my knowledge of microprocessor manufacturing from my days in school, so I won't even begin to speak to specific numbers.

 

[maddie]

I get that the details lie in the numbers and that the problem is very technical under the surface. In the end, the heat has to be dealt with somehow, and heat disposal is far from a new issue. Passive migration of heat from the cores will hit hard limits and require active intervention to remove it. It may even require microscopic channels moving coolant in a closed loop inside of the chips themselves. The industry long moved past my knowledge of microprocessor manufacturing from my days in school, so I won't even begin to speak to specific numbers.

Agreed that heat density is a big limitation to progress. I remember some time ago reading about that as a possible solution. I think channel erosion was an issue in experiments.

 

[Doug S]

Agreed that heat density is a big limitation to progress. I remember some time ago reading about that as a possible solution. I think channel erosion was an issue in experiments.

Are there fluids they can efficiently pump through such tiny channels? Channel erosion was probably caused by having to use too much pressure because of viscosity/surface tension type issues trying to pump through "pipes" with such a small cross section.

It might also be caused by not having gentle bends in those channels but rather more like a 90* turn. They can obviously drill tiny holes in the right places but need a horizonal channel so that one tiny hole is "in" and the other is "out". They could add a horizontal channel during fabrication but adding gentle bends from it to where the holes are drilled sounds way harder. If there was a way to drill all the way through the entire chip and pump the fluid from the socket to the top of the chip it would work better since it would be a straight shot but that would certainly complicate motherboard design lol