Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[RTX]

Since this was one of the biggest issue with BSPDN, it came up in the beginning and when asked, Intel did mention that they've solved it (but didn't share more info). If BSPDN still has such a fundamental issue, both TSMC & Intel wouldn't have bothered to adopt it in the first place.

In fact Panther Lake for laptops is coming out next year with BSPDN. So, both Intel's PowerVia and TSMC's SPR can't be that bad.

PowerVia has thermal mitigations unlike SPR ( tomshardware quotes TSMC director )

 

[Hitman928]

PowerVia has thermal mitigations unlike SPR ( tomshardware quotes TSMC director )View attachment 112315

What part of the screenshot talks about the thermal mitigations?

 

[SiliconFly]

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[FlameTail]

Even with that crutch, A16 is going to be a better node than 18A across the board: performance, power and area.

We already know that A16 has denser SRAM cells;
18A = 0.021μm²
A16 = 0.0175 μm²

 

[SiliconFly]

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[maddie]

Are there fluids they can efficiently pump through such tiny channels? Channel erosion was probably caused by having to use too much pressure because of viscosity/surface tension type issues trying to pump through "pipes" with such a small cross section.

It might also be caused by not having gentle bends in those channels but rather more like a 90* turn. They can obviously drill tiny holes in the right places but need a horizonal channel so that one tiny hole is "in" and the other is "out". They could add a horizontal channel during fabrication but adding gentle bends from it to where the holes are drilled sounds way harder. If there was a way to drill all the way through the entire chip and pump the fluid from the socket to the top of the chip it would work better since it would be a straight shot but that would certainly complicate motherboard design lol

Chemical interactions. Hell, water is pretty much a universal solvent, and when you're dealing with flowing fluid at higher temps constrained by thin films = troublesome.

 

[maddie]

PowerVia has thermal mitigations unlike SPR ( tomshardware quotes TSMC director )

I find this a (strange?) interpretation.



Here is one side of the debate and some comments.



Thanks for the clarification. I can see why Intel "BSPD-only" has an area advantage over TSMC "BSPD compatible with FSPD", but doesn't that also make an assumption about how the BSPD contacts are made -- I thought that Intel's were offset from the transistors which means they need some extra area, where TSMC's come up directly underneath, have your ares estimates allowed for this?

As you say, TSMC have a very strong commercial drive to make cell libraries compatible between FSPD N2 and BSPD A16 -- IP in the sense of higher level macros is only compatible if it's relaid out with the new PDN, so "high-level" IP like SERDES macros (which have a huge development effort/time) won't be compatible. There are other reasons with staying with FSPD such as lower cost and much less of a hot-spot problem, which is why TSMC only reccomend A16 for "actively cooled HPC devices" -- meaning where the heatsink/cooling plate can be kept cold enough (e.g. no more than 60C). This is a massive downside which excludes BSPD for many applications, including ours.

(I've simulated worst-case hot-spot temperature rises from +20C with N2 (FSPD) to +50C with BSPD, which means the die has to be kept 30C cooler to keep within EM and reliability limits,

That means Intel may be excluded from a lot of applications if they are BSPD-only, and may force TSMC to support both FSPD and BSPD well beyond N2/A16. That's not a big process/support issue since all the difficult/expensive/fine-pitch bits (FEOL/MEOL/BEOL up to top metal layers) are the same, only the thick metal layers and TSVs are different -- but this could prevent TSMC from going "BSPD-only", unless they fork the IP/libraries into BSPD-only and FSPD variants which is a *lot* of effort -- not just for TSMC but also all the 3rd party IP suppliers, including the digital library suppliers that many customers (including us ) use.

My guess is that they'll do this at some point (A14? Axx), when there's a big enough demand for BSPD and the IP optimized for it -- but will continue to support FSPD for applications that can't switch, which I expect is a large number.

We are being told directly that Intel has the same heat mitigation issues and this will prevent its use by many customers. He see NO difference between Intel and TSMC in this issue.

It says "The major impediment for A16 is not being able to delete the FSPDN power rails due to backwards compatibility with TSMC N2". This is the main problem with TSMC A16. Hence it requires active cooling and is suitable for only certain use cases. Not suitable for most client products by Apple M series, Intel Core Ultra, AMD Zen series, Nvidia consumer dGPUs, etc.

In short, TSMC A16 is total c%@p.

Nope. He's saying that the design libraries are setup to use both BSPD & FSPD which translate to FSPD spacing by default. There will be no FSPD power rails in a BSPD design and vice versa.

Note the claim that Intel may be excluded from many applications because of the heat issues. The opposite of your "interpretation" that this a TSMC issue only.

Accounting for your posting history, I will say this. You should be very concerned for Intel foundry if that issue is real as the potential client list has contracted significantly.

Also, you miss the huge advantage TSMC is giving clients. Flexibility in using BSPD & FSPD for a given design effort. I can even see a design using FSPD for lower power applications and that same design with a few mods being used in a HPC situation by changing from FSPD to BSPD power delivery. Sounds like AMD and its design philosophy could do something like this.


Why is anyone taking Intel at face value for claiming they have no issues with heat mitigation, and proselytizing. My personal belief is the attempts/claims are becoming so ridiculous that it might be achieving the opposite effect.

 

[LightningZ71]

I find this a (strange?) interpretation.



Here is one side of the debate and some comments.



Thanks for the clarification. I can see why Intel "BSPD-only" has an area advantage over TSMC "BSPD compatible with FSPD", but doesn't that also make an assumption about how the BSPD contacts are made -- I thought that Intel's were offset from the transistors which means they need some extra area, where TSMC's come up directly underneath, have your ares estimates allowed for this?

As you say, TSMC have a very strong commercial drive to make cell libraries compatible between FSPD N2 and BSPD A16 -- IP in the sense of higher level macros is only compatible if it's relaid out with the new PDN, so "high-level" IP like SERDES macros (which have a huge development effort/time) won't be compatible. There are other reasons with staying with FSPD such as lower cost and much less of a hot-spot problem, which is why TSMC only reccomend A16 for "actively cooled HPC devices" -- meaning where the heatsink/cooling plate can be kept cold enough (e.g. no more than 60C). This is a massive downside which excludes BSPD for many applications, including ours.

(I've simulated worst-case hot-spot temperature rises from +20C with N2 (FSPD) to +50C with BSPD, which means the die has to be kept 30C cooler to keep within EM and reliability limits,

That means Intel may be excluded from a lot of applications if they are BSPD-only, and may force TSMC to support both FSPD and BSPD well beyond N2/A16. That's not a big process/support issue since all the difficult/expensive/fine-pitch bits (FEOL/MEOL/BEOL up to top metal layers) are the same, only the thick metal layers and TSVs are different -- but this could prevent TSMC from going "BSPD-only", unless they fork the IP/libraries into BSPD-only and FSPD variants which is a *lot* of effort -- not just for TSMC but also all the 3rd party IP suppliers, including the digital library suppliers that many customers (including us ) use.

My guess is that they'll do this at some point (A14? Axx), when there's a big enough demand for BSPD and the IP optimized for it -- but will continue to support FSPD for applications that can't switch, which I expect is a large number.

We are being told directly that Intel has the same heat mitigation issues and this will prevent its use by many customers. He see NO difference between Intel and TSMC in this issue.



Nope. He's saying that the design libraries are setup to use both BSPD & FSPD which translate to FSPD spacing by default. There will be no FSPD power rails in a BSPD design and vice versa.

Note the claim that Intel may be excluded from many applications because of the heat issues. The opposite of your "interpretation" that this a TSMC issue only.

Accounting for your posting history, I will say this. You should be very concerned for Intel foundry if that issue is real as the potential client list has contracted significantly.

Also, you miss the huge advantage TSMC is giving clients. Flexibility in using BSPD & FSPD for a given design effort. I can even see a design using FSPD for lower power applications and that same design with a few mods being used in a HPC situation by changing from FSPD to BSPD power delivery. Sounds like AMD and its design philosophy could do something like this.


Why is anyone taking Intel at face value for claiming they have no issues with heat mitigation, and proselytizing. My personal belief is the attempts/claims are becoming so ridiculous that it might be achieving the opposite effect.

Your second to last paragraph, that matches up well with the rumors that soon AMD will separate client CCDs from Server/DC CCDs. If one has to use FSPD for thermal related issues and the other doesn't, that could make for an interesting split.

 

[RTX]

TSMC starts equipment installation for 2nm fab - Taipei Times

Bringing Taiwan to the World and the World to Taiwan

www.taipeitimes.com

Demand for A16 is also “very high” for AI server chip production, “so we are working very hard to prepare both 2-nanometer and A16 capacities.”

The 2-nanometer chips would be primarily used in smartphones and high-performance computing applications, the company said.

Apple Inc and Micro Devices Inc are likely to be among the first adopters of TSMC’s 2-nanometer chips.
tomshardware

 

[igor_kavinski]

Your second to last paragraph, that matches up well with the rumors that soon AMD will separate client CCDs from Server/DC CCDs. If one has to use FSPD for thermal related issues and the other doesn't, that could make for an interesting split.

Very astute observation!

 

[RTX]

https://forums.anandtech.com/attachments/tsmc-a16-png.110157/

https://forums.anandtech.com/attachments/n2p-a16nanoflex-png.110158/

Same layout footprint as N2P ( same transistor density )

"The logic layout migration from N2P to A16 is actually quite straightforward because the cell structure and most of the layout patterns are quite the same," said Wang. "So, besides keeping the same front side structure, the beauty of A16 is that it inherits the NanoFlex feature from N2 device width modulation for the maximum driving strength."

https://images.anandtech.com/doci/21369/tsmc-a16-spr.png

https://forums.anandtech.com/attachments/samedimensions-png.110159/

https://forums.anandtech.com/attachments/a16utilization-png.110160/

~10% increase via better utilization

https://forums.anandtech.com/attachments/powervia-png.108575/

https://images.anandtech.com/doci/18894/PowerVia%20Technical%20Deck_15.png

PowerVia inline with increased voltage/frequency as non PowerVia designs

 

[Doug S]

In short, TSMC A16 is total c%@p.

That's not how I read it at all. A16 is BSPDN only which is fine, if you don't want BSPDN you use N2. So N2P & A14 are likely to be "twins" in the same way. They let customers choose.

Sounds to me like Intel's way is inferior as you have no choice in the matter which may cost them some customers until the heat thing is worked out. But given their lesser resources than TSMC they probably decided maintain two foundry tracks was not worth the additional cost/effort and since they want backside power for their own chips that's the obvious track to hitch their wagon to.

 

[RTX]

Nope. He's saying that the design libraries are setup to use both BSPD & FSPD which translate to FSPD spacing by default. There will be no FSPD power rails in a BSPD design and vice versa.

SiliconFly might've missed that Kevin Zhang interview

https://forums.anandtech.com/attachments/tsmc-a16-png.110157/

 

[maddie]

SiliconFly might've missed that Kevin Zhang interview

https://forums.anandtech.com/attachments/tsmc-a16-png.110157/

So did I.

There is no way anyone could come to his conclusions on reading the exchange, except to promote FUD as an end goal.

 

[SiliconFly]

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[maddie]

Don't talk abt me. No one spreads more Intel FUD than you.

The word was "anyone". Did I mention you by username? Don't blame me for your sensitivities. You, on the other hand, have mentioned me. What now?

 

[SiliconFly]

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[maddie]

You've always been critical of me and have been targeting me for a while, while I've been very patient with you. Please feel free to ignore my posts if you don't like them instead of being passive aggressive and throwing veiled insults.

Good lord man, I've responded to your posts, not YOU. If you write something I disagree with, I have the option to respond and say why I think you're wrong/mistaken. I always argue for my interpretation as you do for yours. The free battle of opinions and ideas. It just happens that I find a lot of your arguments & conclusions simply wrong.

If you feel insulted, please don't, it's not my intention. Having said that, I won't hold back on commenting.

 

[SiliconFly]

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[SiliconFly]

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[ajsdkflsdjfio]

We are being told directly that Intel has the same heat mitigation issues and this will prevent its use by many customers. He see NO difference between Intel and TSMC in this issue.

Told directly by who, the great IanD of semiwiki forums?? He claims to be someone who works on semiconductor circuits but I don't think that makes him qualified enough to give an accurate opinion on the effects of bspd on heat and especially not enough to compare the completely proprietary bspd implementations of Intel and TSMC. By the way, RTX is not referring to IanD's post when he made those initial remarks, he was referring to nghanayem's postings which referred to the idea that intel's powervia bspd is more mature than TSMC's version since they already had it tested on intel4 with positive results. nghanayem also referenced the intel4+powervia vs intel4 thermal findings and agreed that it's likely dressed up:

"probe temperatures in line with base intel 4 data running at 3 GHz and 1.1V. Sure, I'm sure the data it's dressed up, but even when you dress up data you can't get results that good without there being some secret sauce at work"

I don't know how much the results are from fluff vs actual innovations but I'd tend to give intel at least a little bit of credit.

Why is anyone taking Intel at face value for claiming they have no issues with heat mitigation, and proselytizing. My personal belief is the attempts/claims are becoming so ridiculous that it might be achieving the opposite effect.

I doubt the vast majority of people actually take intel's findings as fact. Obviously everybody knows that any company promotional detail has some caveat in testing methodology or some other factor that fudges up the data. I do however think that a wise person wouldn't just completely discredit the data and treat it as if it's 100% falsified information. You can't just outright claim intel's BSPD implementation is going to be a trainwreck and will likely cause them to lose tons of customers outside of HPC. Even disregarding your brazen prediction with 0 actual technical knowledge, it's a fact that GPC 18a products are coming out within the year and not only that but in mobile-oriented parts. OFC no one is claiming 18a will be in smartphones anytime soon, but you can't immediately place the blame on intel's powervia implementation. Intel's nodes have always been more focused on performance rather than density or ppw so ofc 18a might not be as good as N2 or even N3 for extreme mobile parts.

Nope. He's saying that the design libraries are setup to use both BSPD & FSPD which translate to FSPD spacing by default. There will be no FSPD power rails in a BSPD design and vice versa.

I don't think that's what he is saying at all. Quoting nghanayem's post (which RTX and SiliconFly were referring to):

"SMC said SPR is optional on A16 and that N2 IPs are drop in compatible. This indicates that A16 uses standard cells with the same size as N2, and that the M0/M2 power rails are still there"

Why would he emphasize the fact that the power rails are still present in A16 and go on further to say that you can't delete them if they were actually optional depending on the library used??? I'm not saying he's right, but obviously he isn't claiming what you are claiming.

Accounting for your posting history, I will say this. You should be very concerned for Intel foundry if that issue is real as the potential client list has contracted significantly.

Firstly the heat issue and it's supposed lack of solutions is speculation by people who largely don't have a good idea of what they are talking about. It may or may not exist but there is already strong empirical evidence that the heat is in fact a non-issue, actual mobile 18a products coming out very soon and much more products planned. Secondly, how are you even sure that 18a doesn't have a FSPD version of the node??? According to my brief research 18a has both BSPD and FSPD libraries, although I may be wrong about this since there is very little actual evidence.

 

[SiliconFly]

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[oak8292]

I think this is the post that started it all. Some snippets:

• "TSMC said SPR is optional on A16 and that N2 IPs are drop in compatible. This indicates that A16 uses standard cells with the same size as N2, and that the M0/M2 power rails are still there (hence preventing any compaction of the cell height). It is for this reason why I call it a partial implementation as opposed to 18A which is BSPDN only and so it gets all the benefits rather than just a good chunk of them."
• "The major impediment native to A16's implementation is not being able to delete the power rails due to the need to support FSPDN and be backwards compatible with N2".

Also, I saw a picture on another forum that depicts the same, but in very high clarity. Not able to locate it now (but will keep looking).

Ian's video, Kevin's answer, SemiWiki posts, all point to one thing very clearly. A16 is not for everyone. For example, a hypothetical CPU on A16 may have hotter hotspots than the same CPU on N2. Looks like all major customers are going to be on N2 and not A16.

Like I said before, A16 is more of a pipe cleaner for TSMC that derisks BSPDN for them and will help them ease in and onboard customers to BSPDN in the future.

From Ian’s interview.

“Q: So if somebody chooses the A16 node, do they have to take the Super Power Rail with it?

A: A16 by definition will have Super Power Rail, yes.”

I think the confusion is whether A16 is a variant of N2 or a new node. From what I read A16 is a high cost variant of N2 for HPC and AI. The optionality of not using SPR is to stay with the lower cost N2 and the expectation is that smartphone die which are cost sensitive and lower power will not move to A16. These nodes will be made in the same fab with the same equipment.

The ‘mobile’ term incorporating both laptops and smartphones is problematic. A PC laptop may operate at 35 watts with higher short term bursts. This doesn’t really work on smartphones.

In my mind one of Intel’s big issues is that their process design is focused on the PC market which has been essentially stagnant for 10 years. PCs peaked at 400 million per year back in the netbook days, pre tablets.

‘Mobile’ or smartphones with power budgets below 10 watts grew to billions per year with small dense die that run at lower frequencies on lower cost processes.

 

[maddie]

I think the confusion is whether A16 is a variant of N2 or a new node. From what I read A16 is a high cost variant of N2 for HPC and AI. The optionality of not using SPR is to stay with the lower cost N2 and the expectation is that smartphone die which are cost sensitive and lower power will not move to A16. These nodes will be made in the same fab with the same equipment.

That's my understanding also. A16 = N2 with BSPD/SPR.

 

[ajsdkflsdjfio]

The ‘mobile’ term incorporating both laptops and smartphones is problematic. A PC laptop may operate at 35 watts with higher short term bursts. This doesn’t really work on smartphones.

In my mind one of Intel’s big issues is that their process design is focused on the PC market which has been essentially stagnant for 10 years. PCs peaked at 400 million per year back in the netbook days, pre tablets.

I agree, mobile smartphones and laptops are completely different classes of products akin to laptop vs desktop. It's pretty clear TSMC will still be the breadwinner for the extreme mobile segment (smartphones, tablets etc), but I think the fact that intel is now using their new 18a node for panther lake, a mobile ultrabook oriented product, instead of TSMC N3B like for lunar lake is a good sign that intel is making headway towards not just higher performance but also density and ppw in their node offerings. Besides, data center is now the new growing segment and I think there is a strong case for 18a's use in data center. Minus the heat complications of powervia, all of intel's new technologies(ribbonfet powervia) provide better transistor density and ppw which are key to data center applications.