Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[jdubs03]

Layout efficiency improves by 5-10% it says. I'm very sure the 30% numbers includes this. They can't scale down anymore. For most structures the ~15-20nm size is a physical limit.

The once-in-a-lifetime changes like BSPD improving density by mere 5-10% is proof of end of Moore's Law. Cutting edge will still love to have it, but computer prices have been increasing for over a decade now, when previous to it the prices declined rapidly. I remember $7000 Dell Desktop ads in the early 2000's.

What comes next then? Once we’re into angstrom. New materials? Quantum?

 

[DavidC1]

What comes next then? Once we’re into angstrom. New materials? Quantum?

No we go from nanowires(GAA) to stacking them, and then doing wafer to wafer and then die to wafer. I also think there's stacking N and P.

https://twitter.com/x/status/1145449871593226242

Of course it greatly increases complexity and even thermal issues, it's not free, we aren't in the 90s anymore.

Pitch scaling is essentially dead. It'll be slow as DRAM. Where we had "10nm class" for 10 years. From 10 Alpha to 10 Beta and so on. That means 10A is 19nm, and 10B is 18nm and so on. But 2x scaling eventually from that is probably doable too. Little by little.

 

[jdubs03]

No we go from nanowires(GAA) to stacking them, and then doing wafer to wafer and then die to wafer. I also think there's stacking N and P.

https://twitter.com/x/status/1145449871593226242

Of course it greatly increases complexity and even thermal issues, it's not free, we aren't in the 90s anymore.

Pitch scaling is essentially dead. It'll be slow as DRAM. Where we had "10nm class" for 10 years. From 10 Alpha to 10 Beta and so on. That means 10A is 19nm, and 10B is 18nm and so on. But 2x scaling eventually from that is probably doable too. Little by little.

Probably would be good to scout IMEC since they’re typically on the leading edge of research.

 

[NostaSeronx]

New node FDSOI ramp-up should have restarted.
18FDS = 100CPP/64Mx, 2025, markets for HPC, Automotive, Mobile
12FDX = unknown if there has been any modification from 84CPP/56Mx, but has been shifted to 2026, same markets as above.

However, the event of Malta and Germany getting FDX puts 12FDX coming out sooner for NA/EMEA than the timeline told to the Asia market.

There is still room for 12FDX launching early on eSoC.3 and a 12FDX+ launching on Advanced SOI (formally, eSoC.3+).

 

[RTX]

Are they going to move to GAA variants at some point?

 

[NostaSeronx]

View attachment 111342
Are they going to move to GAA variants at some point?

It should happen after the market 3nm node. However, there is research pushing the actual planar FDSOI gate length down to 7nm/5nm/3nm. So, it can appear in the market angstrom nodes as well.

mid-2025+ = 10nm FDSOI risk at Fames coalition
2027+ = 7nm FDSOI risk at Fames coalition
2029+ = 5nm FDSOI (Lg=12nm, Leff=9nm, just if anyone is wondering)
2031+ = 3nm FDSOI
2033+ = 2nm GAA or 2nm FDSOI structure that can break Lg=10nm

~~~ image ~~~
~$20B investment by Mubadala/GF for 14XM/14LPP/10XM/10LP/7LP only for them to still be on 14LPP-gen. While the investment in FDSOI is largely based on the long-term agreements, guaranteed revenue from design wins. Where it has surpassed FinFET via the same arrangement with: GF 22FDX+ platform which is seeing broad industry acceptance with more than $7.5 billion in design wins worldwide. How fast 22FDX has been growing; $2B by 2018, $4.5B by 2020, $7.5B by 2021 of design-win revenue. Whereas the FinFET design win revenue; 14LPP/12LP only had $4B by 2019. Since, they haven't updated this number post-pivot, growth of FinFET design wins is likely slower than FDSOI design wins. A lot of the AI/ML group for FinFETs have shifted to Samsung instead.

SOITEC has been reducing the cost of FDSOI wafers by -7% yearly since 2017 as they ramp up production. The cost drawback is old news.

 

[RTX]

They'll skip FDSOI Finfets for FDSOI GAA post 2nm?


Is that 14A in the 2nd pic?

 

[RTX]

A new mim structure

 

[RTX]

@igor_kavinski There's 50% less isolation compared to the TEM in the first pic
18A and beyond won't be stacking plates anymore

 

[DavidC1]

Comparing future Intel vs TSMC nodes. The differences between bleeding edge nodes are becoming very small.

Intel 7 is better than N7 by a small amount, probably 3-5% for performance.
-Intel 4: 20%
-Intel 3: 18%
-Intel 18A: 15%, 18A-P offers 10% over 18A.
-Intel 14A: 15% over regular 18A.

Density wise, 18A roughly N3 level. 14A is 20% better in density over 18A.

TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026

www.anandtech.com

TSMCs 2nm nodes get NanoFlex, N2P loses backside power delivery

TSMC gives an update on 2nm.

www.tomshardware.com

Over N7:
-N5: 15%
-N3E: 18%
-N2P: 15-20%
-A16: 8-10%

Density wise, N2P is 15% over N3E and A16 is 7-10% over N2P.

TTM equalized comparisons:
Intel 3 vs N3E - Intel has 9% speed advantage, and TSMC has 25-30% density advantage.
18A vs N2 - Intel has 8% speed advantage, and TSMC has 15% density advantage
18A-P vs N2P - Intel has 19% speed advantage, and TSMC has 15% density advantage
14A vs A16 - Intel has 9% speed advantage and TSMC has 5-10% density advantage.

 

[RTX]

TSMC 1.6nm update: Tangible improvements, but new challenges emerge

Best suited for AI and HPC processors.

www.tomshardware.com

Ken Wang mentions thermal mitigation issues for A16 and best fit for datacenter-grade AI-aimed processors.

TSMC's says 1.6nm node to be production ready in late 2026 — roadmap remains on track

No, A16 is not delayed, says TSMC.

www.tomshardware.com

TSMC announces customers can now design performance-enhanced 2nm chips with super-high-performance capacitors

N2P IP is ready, all customers can now design 2nm chips, says TSMC.

www.tomshardware.com

 

[dttprofessor]

N2 looks like n3B.

 

[SiliconFly]

.

 

[OneEng2]

Comparing future Intel vs TSMC nodes. The differences between bleeding edge nodes are becoming very small.

Intel 7 is better than N7 by a small amount, probably 3-5% for performance.
-Intel 4: 20%
-Intel 3: 18%
-Intel 18A: 15%, 18A-P offers 10% over 18A.
-Intel 14A: 15% over regular 18A.

Density wise, 18A roughly N3 level. 14A is 20% better in density over 18A.

TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026

www.anandtech.com

TSMCs 2nm nodes get NanoFlex, N2P loses backside power delivery

TSMC gives an update on 2nm.

www.tomshardware.com

Over N7:
-N5: 15%
-N3E: 18%
-N2P: 15-20%
-A16: 8-10%

Density wise, N2P is 15% over N3E and A16 is 7-10% over N2P.

TTM equalized comparisons:
Intel 3 vs N3E - Intel has 9% speed advantage, and TSMC has 25-30% density advantage.
18A vs N2 - Intel has 8% speed advantage, and TSMC has 15% density advantage
18A-P vs N2P - Intel has 19% speed advantage, and TSMC has 15% density advantage
14A vs A16 - Intel has 9% speed advantage and TSMC has 5-10% density advantage.

Seems like Intel is still leaning into higher clock speeds over higher density. Seems like a dubious decision for server and laptop (both being power limited applications) while being a better idea for desktop.

Additionally, the cost of the process is going up substantially from N3E to N2 and from Intel 3 to 18A. So it isn't just the equipment cost that is rising rapidly, but also the process cost per wafer that is rising rapidly.

Seems like this is unsustainable.

 

[RTX]

If 14A is 20% chip density over 18A, A16 should only be 3-5% denser than 14A.

 

[RTX]

A16 needs liquid cooling for best results.

 

[Hitman928]

View attachment 112235View attachment 112236View attachment 112237
A16 needs liquid cooling for best results.

Where is this from? It’s not entirely accurate.

 

[lakedude]

View attachment 112235View attachment 112236View attachment 112237
A16 needs liquid cooling for best results.

Greater than 1kw?

 

[igor_kavinski]

AMD granted a glass substrate patent to revolutionize chip packaging — Intel, Samsung, and others racing to deploy the new tech

Originally filed in September, 2021.

www.tomshardware.com

AMD isn't sitting still. Mentions mobile devices. Not confirmed of course but damn if AMD becomes the next Qualcomm

 

[Saylick]

Where is this from? It’s not entirely accurate.

Looks like all of the text comes from this thread, namely from poster IanD: https://semiwiki.com/forum/index.ph...-the-secret-plan-of-intel-by-anastasia.20257/

 

[SiliconFly]

.

 

[maddie]

Looks like he's confused "active" cooling with "liquid" cooling. By active cooling I think they actually meant a cpu with a fan, not LN2 or anything.

And I remember reading somewhere recently that SPR is a bit better than PowerVia. And considering Intel has a slew of products coming out with BSPDN next year (including laptop CPUs), BSPDN can't be that bad.

I think he missed something important.

Nope, read it properly.

"The other hidden gotcha is that all this heat has to get out through all the topside metal/oxide layers (instead of backside through the bulk) which have higher thermal resistance, so the transistors (and metal) run considerably hotter compared to the heatsink. Which is OK if you're liquid cooling and can provide a nice cold cooling plate, but not so good with air cooling in many applications where the heatsink runs a lot hotter."

Makes complete sense to me.

BSPD allows more power to the transistors which then generate more heat (duh).Then, because they're effectively more insulated due to additional metal/oxide layers between the heat producing switching elements and the cooling plate, you want the highest ∆T possible. Air cooling is worse than liquid for keeping the cooling plate at lowest temps.

Not doing this reduces the power & performance advantages for devices not optimally cooled, as you have to back off the increased power option.

 

[Doug S]

Nope, read it properly.

"The other hidden gotcha is that all this heat has to get out through all the topside metal/oxide layers (instead of backside through the bulk) which have higher thermal resistance, so the transistors (and metal) run considerably hotter compared to the heatsink. Which is OK if you're liquid cooling and can provide a nice cold cooling plate, but not so good with air cooling in many applications where the heatsink runs a lot hotter."

Makes complete sense to me.

BSPD allows more power to the transistors which then generate more heat (duh).Then, because they're effectively more insulated due to additional metal/oxide layers between the heat producing switching elements and the cooling plate, you want the highest ∆T possible. Air cooling is worse than liquid for keeping the cooling plate at lowest temps.

Not doing this reduces the power & performance advantages for devices not optimally cooled, as you have to back off the increased power option.

Would atomically thin oxide layers really change the overall thermal resistance that much? If so, someone needs to turn that into a house paint so you can paint yourself to a higher R value!

 

[Saylick]

Would atomically thin oxide layers really change the overall thermal resistance that much? If so, someone needs to turn that into a house paint so you can paint yourself to a higher R value!

Apparently it does, which is why AMD put the V-cache die under the CCD for Zen 5 X3D.

 

[SiliconFly]

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