Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[dullard]

TSMC has been clear that they don't see a role for high NA until A10, and it isn't even certain they will use it then as they've suggested it is possible it won't become a necessity until A7 (or maybe they will do for A10 like they did for N7, where that was DUV only, then they introduced N7+ that used EUV for a few critical layers)

There is a big overlap between lithography equipment's capabilities. Yes, older equipment can do the same thing as newer equipment--to a certain extent. The difference is complexity. The older equipment needs more masks, more complex patterning (double then eventually quadruple patterning), more cycle time. All which ends up with lower yield and less throughput.

According to ASML, high-NA is less complex starting at about 2 nm node scale. That doesn't mean that standard EUV won't work though. It comes down to a tradeoff: price of the high-NA EUV equipment vs higher complexity of standard EUV equipment.

https://cdn.mos.cms.futurecdn.net/4QRusGRAvSZLBs96sMUZJk-970-80.png.webp

If you have a new machine that costs twice as much and at best does the work of two old machines (i.e. double patterning) then you aren't saving anything, and are incurring additional risk since the new machine is, well, new. TSMC seems happy to let Intel work out its teething problems for now.

Plus even if it more than lives up to its promises and Intel is able to take the process lead or the wafer cost lead that would hardly affect TSMC. Intel cannot come close to competing with TSMC's scale, and TSMC is booking new fabs out a year as fast as they can build and equip them. Even if Intel could afford to build fabs at enough scale to worry TSMC, ASML won't be able to ship enough high NA machines fast enough for it to matter in the 14A/A14 generation.

TSMC does need to worry about falling into the same trap Intel did with EUV. Intel was in the lead, decided not to invest in EUV early, and then Intel was trampled by TSMC. Now Intel can't get enough EUV machines to meet their needs. I hope TSMC does not fall into that same complacency.

 

[511]

TSMC does need to worry about falling into the same trap Intel did with EUV. Intel was in the lead, decided not to invest in EUV early, and then Intel was trampled by TSMC. Now Intel can't get enough EUV machines to meet their needs. I hope TSMC does not fall into that same complacency.

TSMC won't though cause they have multiple customers there can be issues though

 

[sdifox]

TSMC is mulling upgrading to 4nm in Japan Fab2

https://www.tomshardware.com/tech-industry/semiconductors/tmsc-ponders-upgrading-2nd-japan-fab-to-4nm-could-pave-the-way-for-more-advanced-chips-for-japanese-customers

 

[dullard]

TSMC won't though cause they have multiple customers there can be issues though

Hopefully. TSMC isn't on the 2026 or 2027 delivery list as far as I know. That puts them into delivery in 2028 (and production probably not until later).

ASML Schedules Delivery of 56 Low-NA and 10 High-NA EUV Tools in 2027

ASML is about to manufacture significantly more Low-NA EUV and High-NA EUV machines than it originally anticipated. As you may be aware, acquiring an EUV scanner is a year-long process, during which companies make commitments that can span several years to procure these tools. According to ASML...

www.techpowerup.com

 

[Doug S]

No foundry shares this part Intel won't share the recipe and likewise another foundry even if they figure out teething problems they won't do it for others.

Of course the foundries don't share lessons learned on new equipment with other foundries. But these are fantastically complex devices and much of that work is done in cooperation with ASML. Fixes or service notes on the ASML side will go out to everyone, even if it was Intel who uncovered the problems first and has some further proprietary information they aren't sharing (sort of like how TSMC figured out EUV pellicles for themselves)

Lessons learned on the first gen high NA scanner feed back into the next gen high NA scanner. In fact, this has already happened since Intel has a second gen high NA scanner now that incorporated findings from the first gen low volume not mass production ready version. By the time TSMC introduces high NA for mass production it will be done on the third possibly even fourth generation high NA. Problems encountered by Intel ramping up mass production on the second gen will be fed back into future generations, increasing their reliability and "on" time.

 

[jdubs03]

Not sure this is the greatest idea:

https://www.tomshardware.com/tech-industry/semiconductors/taiwan-considers-tsmc-export-ban-that-would-prevent-manufacturing-its-newest-chip-nodes-in-u-s-limit-exports-to-two-generations-behind-leading-edge-nodes-could-slow-down-u-s-expansion

It’s a bit iffy on how they’d describe generation. As they could include N3B, N3E, N3P are all in the same 3nm gen. And would A16 be considered 2nm? If so that would be worst case.
And if it happens, it puts even more onus on Intel to succeed with 18A/P, 14A. (Maybe that Ohio plant gets pulled back in a year or so?

 

[Thunder 57]

Not sure this is the greatest idea:

https://www.tomshardware.com/tech-industry/semiconductors/taiwan-considers-tsmc-export-ban-that-would-prevent-manufacturing-its-newest-chip-nodes-in-u-s-limit-exports-to-two-generations-behind-leading-edge-nodes-could-slow-down-u-s-expansion

It’s a bit iffy on how they’d describe generation. As they could include N3B, N3E, N3P are all in the same 3nm gen. And would A16 be considered 2nm? If so that would be worst case.
And if it happens, it puts even more onus on Intel to succeed with 18A/P, 14A. (Maybe that Ohio plant gets pulled back in a year or so?

It's not a good idea. I don't know how true it is because rumor is now Japan is getting N2. Also, if they did this the US might tell them to kick rocks if China pulls anything, or throw more money at IFS.

 

[DZero]

It's not a good idea. I don't know how true it is because rumor is now Japan is getting N2. Also, if they did this the US might tell them to kick rocks if China pulls anything, or throw more money at IFS.

Talking about China...

China eyes mastery of EUV lithography, bolstering AI chip ambitions: analysts

‘As the semiconductor dream has become a national security issue, I would not underestimate China’s ambition,’ Natixis analyst Gary Ng says.

www.scmp.com

https://www.reuters.com/world/china/how-china-built-its-manhattan-project-rival-west-ai-chips-2025-12-17/

Expect that by 2027 they pull their EUV at 5 or 4nm, but with that is enough to deliver a BIG hit for the rest.

Even more, right now managed to pull 5nm on their DUV and Huawei is the user of it, still, only has 1 generation left and that's all for their DUV project.

 

[jdubs03]

Talking about China...

China eyes mastery of EUV lithography, bolstering AI chip ambitions: analysts

‘As the semiconductor dream has become a national security issue, I would not underestimate China’s ambition,’ Natixis analyst Gary Ng says.

www.scmp.com

https://www.reuters.com/world/china/how-china-built-its-manhattan-project-rival-west-ai-chips-2025-12-17/

Expect that by 2027 they pull their EUV at 5 or 4nm, but with that is enough to deliver a BIG hit for the rest.

Even more, right now managed to pull 5nm on their DUV and Huawei is the user of it, still, only has 1 generation left and that's all for their DUV project.

I am highly skeptical that this would be achievable. They have one prototype (much larger in size than a typical ASML machine) that they expect to be producing test chips by 2028 at the earliest according to that article. Let alone having a fully built infrastructure and supply chain for HVM.

 

[DZero]

I am highly skeptical that this would be achievable. They have one prototype (much larger in size than a typical ASML machine) that they expect to be producing test chips by 2028 at the earliest according to that article. Let alone having a fully built infrastructure and supply chain for HVM.

Indeed, but the same was said about Chinese way to reach 5nm with DUV and look at them. So we can't discard nothing anymore.

 

[Win2012R2]

I am highly skeptical that this would be achievable.

Given the stakes it's only a question when, it's getting close since they are now having leaks

 

[511]

Not sure this is the greatest idea:

https://www.tomshardware.com/tech-industry/semiconductors/taiwan-considers-tsmc-export-ban-that-would-prevent-manufacturing-its-newest-chip-nodes-in-u-s-limit-exports-to-two-generations-behind-leading-edge-nodes-could-slow-down-u-s-expansion

It’s a bit iffy on how they’d describe generation. As they could include N3B, N3E, N3P are all in the same 3nm gen. And would A16 be considered 2nm? If so that would be worst case.

basically whatever is in HVM in taiwan can't be exported to other countries they will get N-1
N3 family
N2 Family
A16
A14 like that

And if it happens, it puts even more onus on Intel to succeed with 18A/P, 14A. (Maybe that Ohio plant gets pulled back in a year or so?

Ohio Pull back is something time will tell

 

[jdubs03]

basically whatever is in HVM in taiwan can't be exported to other countries they will get N-1
N3 family
N2 Family
A16
A14 like that

Ohio Pull back is something time will tell

That’s how it has been but that article implies N-2. A16 is where I get hung up a bit because it’s basically N2P with backside power delivery. But since it’s A and not N, perhaps they consider a different class altogether.

 

[Joe NYC]

basically whatever is in HVM in taiwan can't be exported to other countries they will get N-1
N3 family
N2 Family
A16
A14 like that

Ohio Pull back is something time will tell

Of the 4 entities:
- Taiwan government
- TSMC management
- US government
- US fabless customers

This came from the least important of the 4 entities, Taiwan government.

 

[511]

Of the 4 entities:
- Taiwan government
- TSMC management
- US government
- US fabless customers

This came from the least important of the 4 entities, Taiwan government.

Don't forget TSMC is a Taiwan Companies so their order has value and they are a stakeholder in TSMC as well

 

[Doug S]

Indeed, but the same was said about Chinese way to reach 5nm with DUV and look at them. So we can't discard nothing anymore.

Why would anyone be skeptical of being able to achieve 5nm with DUV? I certainly wasn't. TSMC did for 7nm, and China had access to new and improved DUV machines that didn't exist when TSMC was running N7 wafers on DUV only. They are also in a position where they don't have EUV so they have no choice but to find a way to make it work even if it means reduced yields and expensive wafers. TSMC probably could have made DUV work for N5 if EUV wasn't available, but they didn't have to try.

Running 5nm wafers on DUV with heroic multipatterning is a TOTALLY different matter than making a whole new EUV machine work for mass production. Recall that ASML had EUV scanners for years that delivered good results, just far too slow to be cost effective for mass production. If being able to run 5-10 wafers per hour was acceptable we could have had EUV several process generations earlier. It just didn't make sense to use then because it would have been more expensive and we were able to extend DUV's life with multipatterning well beyond what people originally believed when EUV development began.

China has a different value equation, being able to claim EUV production / 2nm / whatever is worth it for national pride even if it costs 10x as much as TSMC per wafer due to low throughput and/or poor yields. They would use it for shall we say "less cost sensitive" markets such as defense, HPC and AI. You wouldn't see Huawei selling phones using those chips, because a $500 smartphone SoC doesn't make financial sense.

If they are in the prototype stage now it could mean they could get it ready for "mass production" (at low rates) within a few years or they could encounter hurdles along the way. We might read about how China is ready to mass produce EUV wafers "next year" year after year. Or we might one day hear they are in mass production, but no one would be able to independently verify that because all the chips for those less cost sensitive markets will be behind locked doors in datacenters or in military gear, not shipping in products anyone could get their hands on for a teardown.

 

[desrever]

Why would anyone be skeptical of being able to achieve 5nm with DUV? I certainly wasn't. TSMC did for 7nm, and China had access to new and improved DUV machines that didn't exist when TSMC was running N7 wafers on DUV only. They are also in a position where they don't have EUV so they have no choice but to find a way to make it work even if it means reduced yields and expensive wafers. TSMC probably could have made DUV work for N5 if EUV wasn't available, but they didn't have to try.

Running 5nm wafers on DUV with heroic multipatterning is a TOTALLY different matter than making a whole new EUV machine work for mass production. Recall that ASML had EUV scanners for years that delivered good results, just far too slow to be cost effective for mass production. If being able to run 5-10 wafers per hour was acceptable we could have had EUV several process generations earlier. It just didn't make sense to use then because it would have been more expensive and we were able to extend DUV's life with multipatterning well beyond what people originally believed when EUV development began.

China has a different value equation, being able to claim EUV production / 2nm / whatever is worth it for national pride even if it costs 10x as much as TSMC per wafer due to low throughput and/or poor yields. They would use it for shall we say "less cost sensitive" markets such as defense, HPC and AI. You wouldn't see Huawei selling phones using those chips, because a $500 smartphone SoC doesn't make financial sense.

If they are in the prototype stage now it could mean they could get it ready for "mass production" (at low rates) within a few years or they could encounter hurdles along the way. We might read about how China is ready to mass produce EUV wafers "next year" year after year. Or we might one day hear they are in mass production, but no one would be able to independently verify that because all the chips for those less cost sensitive markets will be behind locked doors in datacenters or in military gear, not shipping in products anyone could get their hands on for a teardown.

They are going to try to do 3nm with multi patterning too. Because they are backed into using multi patterning, they will likely develop much more cost effect ways of utilizing it over time. Anything they learn with multi patterning will be applied to EUV once its available.

Anyways they will likely apply the same playbook as they do with other tech like EVs and Batteries once they have the core technology. Don't expect them to just be happy fabbing high cost wafers for specific applications. Expect them to grow the industry with targeted government support and also expect them to drive local competition to bring the technology costs down over time as well.

 

[LightningZ71]

It was circulated online last week that they had gotten access to an EUV system and done a teardown on it. I'm skeptical, but have zero doubts about their cyber espionage efforts in the industry.

 

[jdubs03]

They were only able to get second order parts. I would imagine the secondary markets could be clamped down on a bit.

I think people underestimate how much work it took for ASML to get to where it has, cultivating a whole supply chain to support their lithography endeavors. Nikon and Canon were stalwarts and couldn’t do it.

Just to establish the timeline, the first ever EUV prototype was created in 2001. It took 18 years to get to HVM. If China could get to something reasonable in a hostile environment where their access to technology to improve and expand is very limited, compressing that 18 into 6 would be an accomplishment.

 

[jpiniero]

They were only able to get second order parts. I would imagine the secondary markets could be clamped down on a bit.

I think people underestimate how much work it took for ASML to get to where it has, cultivating a whole supply chain to support their lithography endeavors. Nikon and Canon were stalwarts and couldn’t do it.

Just to establish the timeline, the first ever EUV prototype was created in 2001. It took 18 years to get to HVM. If China could get to something reasonable in a hostile environment where their access to technology to improve and expand is very limited, compressing that 18 into 6 would be an accomplishment.

Two words: Industrial Espionage.

 

[jdubs03]

Two words: Industrial Espionage.

Yeah I know that. But they’ve been doing it for decades. The article implies it more or less via Chinese nationals “retiring” and then getting massive pay packages.

The technical challenge remains nonetheless very high. Hence my whole last paragraph.

To think they can just speed run to HVM is pretty presumptuous. Secondary parts can only get them so far; particularly with getting to HVM with multiple fabs.

 

[DrMrLordX]

I am highly skeptical that this would be achievable. They have one prototype (much larger in size than a typical ASML machine) that they expect to be producing test chips by 2028 at the earliest according to that article. Let alone having a fully built infrastructure and supply chain for HVM.

As you noted in subsequent posts, the frankensteined machine they have is not something they're able to build from the ground-up all on their own. Even if they do manage to achieve some sort of useful lithography with their machine, they won't be able to scale out.

 

[LightningZ71]

One thing to keep in mind with the very long development of the first generation production scale EUV systems is that part of the process of getting from the initial setup to scale was refining basic physics theories on top of the various improvements to DUV equipment informing the development of EUV systems. China's biggest hurdle is going to be their light source and then making it robust. They're deep into that development. They are the latest and greatest DUV tech and can just iterate from there.

 

[DrMrLordX]

They are the latest and greatest DUV tech and can just iterate from there.

Not if they're sourcing parts from scrapped out machines from other countries etc.

 

[Doug S]

Anyways they will likely apply the same playbook as they do with other tech like EVs and Batteries once they have the core technology. Don't expect them to just be happy fabbing high cost wafers for specific applications. Expect them to grow the industry with targeted government support and also expect them to drive local competition to bring the technology costs down over time as well.

Oh I agree and I've said before the long term effect will be that China is the first to make FEL lithography work which will be significantly better and cheaper than ASML's EUV roadmap. Yes it looks like the west is finally investing a bit in FEL (xLight) but unless it gets some real money behind it we'll be hopelessly behind China and chip fabrication will be another industry they win at.

All that the embargoes and limitations on the tech allowed to be transferred to China has done is made them realize they need to be self sufficient in every relevant technology. And with a command economy they can actually make that happen, while in the west we have big holes in our tech portfolio where China is much cheaper due to either labor cost or economies of scale, so no one is willing to invest without government subsidy (i.e. the "capitalist" version of a command economy)