Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

---------------------------------------------------------------------------------------------------------------------------------------------------


FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[Tigerick]

AMD launches even their best have some drama anyway. Can't wait for the Zen 6 drama to unfold.

Zen 6% ?

 

[DavidC1]

It's possible 18A-P is similar to Intel 3 in that it's basically same as 18A for PC and HPC customers, but has a small variant where the V-F curve is different so it's more optimized for mobile.

Here's Intel's claims for Intel 3.

• Evolution of Intel 4 with 1.08x chip density and 18% performance per watt improvement.2
• Adds denser library, improved drive current and interconnect while benefiting from Intel 4 learnings for faster yield ramp.
• Well-suited for general compute applications.

Normal people thought: "Ah so all variants of Intel 3 has density improvements, and a "denser library" would make it even denser.

Intel marketing thinking: 8% density only applies if you get the "denser library" version otherwise it's same as Intel 4. Their own slide confirmed this!

It's mind boggling how somehow Gelsinger(despite his claims of being a Christian) pushed the limits of shady marketing tactics.

 

[Io Magnesso]

It's possible 18A-P is similar to Intel 3 in that it's basically same as 18A for PC and HPC customers, but has a small variant where the V-F curve is different so it's more optimized for mobile.

Here's Intel's claims for Intel 3.

Normal people thought: "Ah so all variants of Intel 3 has density improvements, and a "denser library" would make it even denser.

Intel marketing thinking: 8% density only applies if you get the "denser library" version otherwise it's same as Intel 4. Their own slide confirmed this!

It's mind boggling how somehow Gelsinger(despite his claims of being a Christian) pushed the limits of shady marketing tactics.

Perhaps 18AP is not just a simple performance enhancement...
It feels like a wide range of customizations.
But with 18A, the density has improved in both high-performance libraries and high-density libraries, right?
I know Intel is a liar, but I think the situation is different from Intel 3.

 

[Doug S]

Zen 6% ?

So you're saying we should wait for Zen 40 to get the performance increase people here were hyping Zen 5 to deliver?

 

[fastandfurious6]

18A mid-small PP architecture

 

[Panino Manino]

Apparently now GlobalFoundies owns MIPS.

MIPS and GlobalFoundries: Powering the Next Wave of Physical AI​

https://mips.com/blog/mips-and-globalfoundries-powering-the-next-wave-of-physical-ai/

 

[igor_kavinski]

So you're saying we should wait for Zen 40 to get the performance increase people here were hyping Zen 5 to deliver?

By claiming 40%, those leakers manifested a max improvement of 21% and average uplift of 8%.

With 60%, they just might get it to 30% max and 12% average

 

[511]

BTW Intel made 1 Million Wafers in US Fabs this does not include outsourcing from TSMC and Ireland from Where MTL was shipped nor Israel which is low by Intel's standard.

https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-04/chips-design-manufacturing-fact-sheet.pdf

 

[marees]

Apparently now GlobalFoundies owns MIPS.

MIPS and GlobalFoundries: Powering the Next Wave of Physical AI​

https://mips.com/blog/mips-and-globalfoundries-powering-the-next-wave-of-physical-ai/

I thought of posting it here, but the thread name mentioned: "leading edge foundries" 🤪

 

[igor_kavinski]

I thought of posting it here, but the thread name mentioned: "leading edge foundries" 🤪

Feel free to start a "Hall of Shame foundries" thread.

 

[johnsonwax]

Feel free to start a "Hall of Shame foundries" thread.

There are so many Intel threads already.

 

[DrMrLordX]

There are so many Intel threads already.

Ohhhh sick burn. You could etch your own wafers with that.

 

[marees]

Feel free to start a "Hall of Shame foundries" thread.

Here is a post for that

GlobalFoundries unveiled plans in May 2017 to build an advanced fabs in Chengdu in two phases: Phase 1 for 130nm/180nm-class nodes and Phase 2 for 22FDX FD-SOI node. The company committed to invest $10 billion in the project, with about a billion invested in the shell alone.

Financial troubles forced GlobalFoundries to abandon the project in 2018 (the same year it ceased to develop leading-edge process technologies) and refocus to specialty production technologies. By early 2019, the site was cleared of equipment and personnel, and notices were issued in May 2020 to formally suspend operations.

The site and unfinished building remained uninhabited for five years before Shanghai Huali Microelectronics Corp. (HLMC), controlled by the Hua Hong Group, announced it would take over the dormant site in mid-2023. HLMC is one of a few Chinese companies that intend to develop a sub-10nm-class fabrication process. However, it is unclear whether the Chengdu fab will be used as its flagship facility. GlobalFoundries’ Chengdu project serves as a rare example of a recovery among China’s stalled semiconductor projects. A rare exception to the numerous failures that China has encountered thus far.

Zombie fabs plague China's chipmaking ambitions, failures burning tens of billions of dollars

28 fabs later

www.tomshardware.com

 

[Io Magnesso]

TSMC is currently
A14 process transistor density target aims at 500 mm2/mtr

 

[Doug S]

TSMC is currently
A14 process transistor density target aims at 500 mm2/mtr

There are some one time gains BSPDN brings you.

Remember that 500 number is an idealized fantasy like all the density numbers they claim. No one obtains remotely near to their claimed densities in a real design, so it has to compared to density claims of previous processes to judge progress, and not by comparing to actual calculated density of an Apple, AMD, etc. chip.

 

[511]

https://twitter.com/x/status/1943880598143090805

 

[RTX]

TSMC is currently
A14 process transistor density target aims at 500 mm2/mtr

A14 is only 20% denser.

https://www.tomshardware.com/tech-industry/tsmc-unveils-1-4nm-technology-2nd-gen-gaa-transistors-full-node-advantages-coming-in-2028

 

[511]

TSMC is currently
A14 process transistor density target aims at 500 mm2/mtr

we will be lucky if A14 breaches 300 mxtor/mm2

 

[oak8292]

we will be lucky if A14 breaches 300 mxtor/mm2

It seems like transistor density is decreasing in importance and power reduction is the target. Depending on volume the cost of the wafer is probably increasing just about as much as the number of transistors. So minimal decrease in the cost of a transistor. A realized reduction of 30% power is significant in a number of applications, mobile and AI.

 

[511]

It seems like transistor density is decreasing in importance and power reduction is the target. Depending on volume the cost of the wafer is probably increasing just about as much as the number of transistors. So minimal decrease in the cost of a transistor. A realized reduction of 30% power is significant in a number of applications, mobile and AI.

the cost of wafer increase is more then supposed PPA improvements though starting with N2

 

[oak8292]

the cost of wafer increase is more then supposed PPA improvements though starting with N2

Typically the price of transistor a function of volume. There can still be cases where a higher cost transistor decreases the cost of ownership by reducing power over the life of the processor.

If costs are just increasing then shrinks are dead, why reduce margin or buy a more expensive processor?

There were a number of people, even Jensen saying that transistor cost were increasing after 28 nm. However with mobile die volumes in the hundreds of millions the cost continue to decrease.

 

[511]

Typically the price of transistor a function of volume. There can still be cases where a higher cost transistor decreases the cost of ownership by reducing power over the life of the processor.

If costs are just increasing then shrinks are dead, why reduce margin or buy a more expensive processor?

Cause there is no competition you don't have a choice if you wanna sell your product it needs to be the best if you have to pay more many will.

There were a number of people, even Jensen saying that transistor cost were increasing after 28 nm. However with mobile die volumes in the hundreds of millions the cost continue to decrease.

Jensen says too many stuff tbh.

 

[oak8292]

Cause there is no competition you don't have a choice if you wanna sell your product it needs to be the best if you have to pay more many will.

Jensen says too many stuff tbh.

Best at what? One of Intel’s issues is that they are pushing for the best at frequency and this is not what got them to their dominant position.

Moore’s Law is mainly about economics and cost. Reducing the cost of ops or flops. If costs aren’t going down the market isn’t expanding and the cost of fabs can’t be covered.

TSMC has been focused on cost and spreading costs over as many customers as possible. Nvidia with the margin it has on its ops may be the last man standing but it needs to reduce its die size if it wants to first on a node.

Back when Jensen made the claim about increasing transistor costs it may have been true for Nvidia, he didn’t have die volume or margin at that time. Now with margin and low cost ops he is ready to take on the world.

Note that TSMC is not rushing to high NA EUV without ensuring it is cost effective.

 

[jpiniero]

Nvidia with the margin it has on its ops may be the last man standing but it needs to reduce its die size if it wants to first on a node.

nVidia hasn't been first on a node in a long time.

Rubin is very likely to use N3P or another variant of it.

 

[oak8292]

nVidia hasn't been first on a node in a long time.

Rubin is very likely to use N3P or another variant of it.

I know that Nvidia hasn’t been first on a node for awhile but they are in the highest growth market, with the biggest need for more energy efficiency and have the highest margins to pay for the next node. At some point they may need to break to smaller multi-die modules for economics and energy efficiency.

Nvidia has deep pockets at $4 trillion in valuation.