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Intel Skylake / Kaby Lake

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Nothingness

Platinum Member
Jul 3, 2013
2,153
398
126
HTPC as in home theater PC with 4K movie playback? No, Skylake is better.
Doesn't it lack HDMI 2.0 and do HTPC-friendly MB have a workaround for this (which exists in the form of an external chip IIUC)?

IMHO if you aim at 4k, you want HDMI 2.0.
 

ShintaiDK

Lifer
Apr 22, 2012
20,395
128
106
Doesn't it lack HDMI 2.0 and do HTPC-friendly MB have a workaround for this (which exists in the form of an external chip IIUC)?

IMHO if you aim at 4k, you want HDMI 2.0.
2 options:
Motherboard with the LSPcon, also known as Thunderbolt.
The fabled DP to HDMI 2.0 converters that should be out anytime now if not already.

You are not going to see native CPU HDMI 2.0.
 

Edrick

Golden Member
Feb 18, 2010
1,909
196
106
Just got my new rig together last night. Not a bad start. I will spend more time tweaking later tonight. Haven't put much effort in as of yet.

6600k on a Gigabyte Z170X-UD5. 4.2ghz at 1.224v (stock). H100i-GTX.

Temps never go past 60C in Prime95 (FMA) runs.

Memory bandwidth beats any Haswell (non-E).


 
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Nothingness

Platinum Member
Jul 3, 2013
2,153
398
126
2 options:
Motherboard with the LSPcon, also known as Thunderbolt.
The fabled DP to HDMI 2.0 converters that should be out anytime now if not already.

You are not going to see native CPU HDMI 2.0.
That means HDMI 2.0 is covered in a way or the other, thanks.
 

phillyman36

Golden Member
Jun 28, 2004
1,676
92
91
If I calculated right with the UPS delivery that would be about $454.78 USD About $100 more plus i have no idea how much those duties and taxes charges would be.

Thanks pISSANt
 

Sweepr

Diamond Member
May 12, 2006
5,151
1,127
131
Launch schedule of mobile Intel Skylake processors



CPU-World said:
Back in May, we published preliminary launch schedule of Intel Skylake mobile processors. The schedule indicated that Intel was going to launch Core i3-6100H, i3-6100U, Core i5-6200U, i5-6300HQ, Core i7-6500U, i7-6700HQ, i7-6820HK and Core M 6Y30, 6Y54 and 6Y75 models in September 2015. They were supposed to be followed by Core i5-6440HQ, Core i7-6820HQ, i7-6920HQ, Xeon E3-1505M v5 and E3-1535M v5 microprocessors in October or November. Core i5-6300U, i7-6600U and Core M 6Y57 processors were planned for January 2016. We recently received information on updated schedule with finalized launch dates, and it seems that introduction dates for some models have been pushed forward by a month or two.
www.cpu-world.com/news_2015/2015081801_Launch_schedule_of_Intel_mobile_Skylake_processors.html

Instead of delaying they pushed forward some models. Looks like Surface Pro 4 will be ready for an October launch.

Also final specs of the first Xeon E3-1500M v5 models thanks to Bench-life:



Bench-life said:
Core i7-6920HQ and Core i7-6820HQ as to 4C8T processor; clock aspect, Core i7-6920HQ and Xeon E3-1535M v5 same for the 2.9GHz, 2.8GHz and Core i7-6820HQ lower than the E3-1505M v5 , actually 2.7GHz.
http://benchlife.info/intel-xeon-e3-1535m-v5-and-e3-1505m-v5-in-list-08192015
 

Burpo

Diamond Member
Sep 10, 2013
4,130
340
126
Just got my new rig together last night. Not a bad start. I will spend more time tweaking later tonight. Haven't put much effort in as of yet.

6600k on a Gigabyte Z170X-UD5. 4.2ghz at 1.224v (stock). H100i-GTX.

Temps never go past 60C in Prime95 (FMA) runs.

Memory bandwidth beats any Haswell (non-E).


Nice! Be sure & let us know other benchmarks please.. Like this one?

http://forums.anandtech.com/showthread.php?t=2443043
 

Enigmoid

Platinum Member
Sep 27, 2012
2,910
31
91
With AVX 3.2 it seems likely that the L1 cache will have to increase (and since intel's caches are inclusive cache size through to L3 will have to increase) as well as double bandwidth again to reach peak performance.

A good example of this can be seen here. Operating on two continuous arrays of doubles. Using Haswell.

http://stackoverflow.com/questions/19621504/haswell-memory-access

Basically AVX performance drops like a rock when data is not in the L1 cache.
Code:
| Event          | Size=1000   | Size=2000   | Size=3000   | Size=4000      

 Time           | 86  ns      | 166 ns      | 734 ns      | 931    ns     
 L1 load hit    | 252,807,410 | 494,765,803 | 9,335,692   | 9,878,121     
 L1 load miss   | 24,931      | 585,891     | 370,834,983 | 495,678,895   
 L2 load hit    | 16,274      | 361,196     | 371,128,643 | 495,554,002  
 L2 load miss   | 9,589       | 11,586      | 18,240      | 40,147        
 L1D wb acc. L2 | 9,121       | 771,073     | 374,957,848 | 500,066,160 
 L1D repl.      | 19,335      | 1,834,100   | 751,189,826 | 1,000,053,544
It is likely that any CPU with AVX3.2 will face large bandwidth problems without doubling L1 bandwidth again. It also looks likely that the L1 size will have to increase for this reason.

With a 512 bit data width (64 bytes) theoretical peak performance of a +/x b=c requires two 64 bit loads and one 64 bit store, twice that of haswell unless AVX3.2 operates in 2 cycles (which would defeat the point of it over AVX2).



Skylake has dramatically improved L2 and L3 bandwidth by ~50%, however, L1 has not seen any changes.

Hopefully this brings some general IPC gains. Intel is long overdue for a L1/L2 overhaul and size increase.
 

ShintaiDK

Lifer
Apr 22, 2012
20,395
128
106
It will be interesting to see the L1 cache changes on Skylake-E/EP/EX in that regard. It was also clear at IDF that client and servers is now going to be split in terms of development targets. So a server core of x uarch will not be the exact same as one of client.
 

JoeRambo

Senior member
Jun 13, 2013
912
645
136
It is likely that any CPU with AVX3.2 will face large bandwidth problems without doubling L1 bandwidth again. It also looks likely that the L1 size will have to increase for this reason.

With a 512 bit data width (64 bytes) theoretical peak performance of a +/x b=c requires two 64 bit loads and one 64 bit store, twice that of haswell unless AVX3.2 operates in 2 cycles (which would defeat the point of it over AVX2).


Skylake has dramatically improved L2 and L3 bandwidth by ~50%, however, L1 has not seen any changes.
Has Intel disclosed L1 read/write numbers? Haswell has enough of resources to pump VMOVDQA's at very nice rate and enough to sustain FMA. Now question is, can you really push Skylake core without AVX512 instructions? Without input from Intel, anything is speculation at this moment.
 

Sweepr

Diamond Member
May 12, 2006
5,151
1,127
131
New articles:

The many tricks Intel Skylake uses to go faster and use less power

All this isn't to say that performance doesn't matter at all, of course. Intel did describe some of the performance changes it has made in Skylake, so while details are limited, we'll start there. For the most part, Skylake brings a series of incremental improvements, making it wider — able to dispatch more instructions at once—and a little better at extracting parallelism. It can fetch and dispatch, in some circumstances, up to six instructions at once, with up to 224 instructions in its out-of-order buffer at once (up from 192 in Haswell).

The ring buffer that Intel uses to connect all the cores in a processor to the GPU, memory controller, and I/O blocks has also been made faster. The company says that its throughput has doubled, enabling higher performance at the same power cost. Alternatively, Skylake can offer the same level of throughput at a reduced power cost, depending on what the current situation requires. The support for DDR4 should increase memory bandwidth.

The eDRAM cache that Intel supported on a handful of Broadwell systems has also been revamped. In Broadwell, each core pair had 1.5MB of level 3 cache, and the eDRAM, when it was included, was a 128MB level 4 cache that held data evicted from the level 3 cache. In Skylake, the level 3 has been bumped up to 2MB per core pair, and the level 4 cache is gone.

Instead of being a level 4 cache, the eDRAM is now what Intel calls a memory side cache. In Broadwell, the eDRAM was notionally connected to level 3, to store data that the level 3 cache no longer had room for. In Skylake, the eDRAM is now connected between the integrated memory controller and the "system agent;" the portion of the processor that handles, among other things, cache coherence (ensuring that different cores see a consistent view of shared data).
http://arstechnica.com/information-technology/2015/08/the-many-tricks-intel-skylake-uses-to-go-faster-and-use-less-power

Skylake’s graphics architecture: Intel is still gunning for dedicated GPUs

http://arstechnica.com/gadgets/2015/08/skylakes-graphics-architecture-intel-is-still-gunning-for-dedicated-gpus



www.heise.de/ct/artikel/IDF-2015-Neue-Stromsparfunktionen-von-Skylake-unter-Windows-10-2786026.html





http://pc.watch.impress.co.jp/img/pcw/docs/716/965/html/15.jpg.html

Shintai this one's for you. :)

Intel Swift Canyon NUC Shown At IDF with Skylake-U CPU and DDR4 Memory!



Earlier this summer our friends over at FanlessTech leaked out a slide that showing that Intel was going to be releasing a pair of Skylake-U power NUCs in the second half of 2015. Other than seeing that leaked Intel roadmap slide three months back we’ve yet to see any real images of the two new Intel Skylake-U based NUCs that are internally codenamed ‘Swift Canyon’ by Intel. The slide got us excited about the imminent release of the Intel 6th Generation Core series NUCs as we’d love to have a little 4″ x 4″ system packing the power of the Intel Skylake-U CPU along with Intel Gen9 graphics (Intel HD Graphics 520) and up to 32GB of dual-channel DDR4 memory support!
Kingston had the Windows Task Manager open and showed the Intel Skylake-U processor in this Swift Canyon NUC was clocked at 2.28GHz, so we assume this is the Intel NUC Kit that will be sold under part number NUC6i5SYK. Actually, it could be powered by either the Intel Core i5-6200U or the Intel Core i3-6100U as both have a base clock frequency of 2.3GHz, so it might be the Core i3 SKU as well. The Kingston HyperX Impact DDR4 SODIMM 16GB (2 x 8GB) kit was running at 2133MHz with 13-13-13-35 Timings with a 1T Command Rate!

Skylake powered Intel NUC? Yes, please with some eDRAM on top! We are looking forward to see the Intel Skylake-U based NUCs coming out later this year! The two Skylake-U Swift Canyon NUCs coming from Intel include a Core i5 model (NUC6i5SYK/NUC6i5SYH) and a Core i3 model (NUC6i3SYK/NUC3i5SYH).
www.legitreviews.com/intel-swift-canyon-nuc-shown-at-idf-with-skylake-u-cpu-and-ddr4-memory_171024#FA72Ptsj81MvRxW5.99
 

JoeRambo

Senior member
Jun 13, 2013
912
645
136
What are actually the use cases of AVX512?
Same as AVX2, but it has incredibly useful stuff that actually help vectorize what was hard (or ungainful) to vectorize before.

Such a shame that they are not releasing it on client stuff.
 

kimmel

Senior member
Mar 28, 2013
248
0
41
With AVX 3.2 it seems likely that the L1 cache will have to increase (and since intel's caches are inclusive cache size through to L3 will have to increase) as well as double bandwidth again to reach peak performance.
You sure that Skylake's caches are fully inclusive?
 

DrMrLordX

Lifer
Apr 27, 2000
16,627
5,634
136
Intel's cache architecture has been fully inclusive for years (so far as I know). Any deviation from that cache layout would probably change cache performance vs Haswell/Broadwell. So far as I know, nobody has come out and said that cache on Skylake is slower than previous generations.
 

cmdrdredd

Lifer
Dec 12, 2001
26,703
248
106
G.skill is showing off new memory at IDF. Does anyone think this stuff is even worth it? Seems like all the super fast memory is not available in 2x8GB either.





 
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