Discussion Intel Nova Lake in H2-2026: Discussion Threads

[Tigerick]

Not much news lately, but found a leak claiming the NVL NPU6 specs are expected to be 74TOPS INT8:

Intel Nova Lake NPU6 Expected To Deliver 74 TOPS Of AI Performance

As per the claim by a prominent leaker, the Intel Nova Lake will boast NPU6 that will deliver up to 74 AI TOPS performance.

wccftech.com

NPU6 should have 80TOPS, like others...

At least it confirms the desktop variant of NVL also will get NPU function.

 

[511]

Not much news lately, but found a leak claiming the NVL NPU6 specs are expected to be 74TOPS INT8:

Intel Nova Lake NPU6 Expected To Deliver 74 TOPS Of AI Performance

As per the claim by a prominent leaker, the Intel Nova Lake will boast NPU6 that will deliver up to 74 AI TOPS performance.

wccftech.com

No one needs this waste of die space 13 Tops would have been enough

 

[Fjodor2001]

No one needs this waste of die space 13 Tops would have been enough

I assume it’s to fulfill the Microsoft Copilot+ PC requirement of 40+ TOPS.

Not sure why they go above that though. Perhaps because they think it won’t be sufficient to get the desired perf for that type of tasks, that the bar will be raised with Win 12, and/or to look good in review benchmarks and comparisons with other CPUs.

 

[dullard]

Not sure why they go above that though. Perhaps because they think it won’t be sufficient to get the desired perf for that type of tasks, that the bar will be raised with Win 12, and/or to look good in review benchmarks and comparisons with other CPUs.

Because doing the bare minimum is always the best approach.

My alternative post was pieces of flair--but that reference is a bit dated.

 

[Fjodor2001]

Funny video. Not sure how it relates to my post though. Apparently Intel is going for above minimum. Perhaps they don’t want to end up at the bottom of the list in review benchmarks, but rather stay in the top.

What would also be interesting to know is what NPU will be included on Zen6 DT, if any. I assume AMD will be going for Copilot+ compliance at least.

 

[regen1]

Not much news lately, but found a leak claiming the NVL NPU6 specs are expected to be 74TOPS INT8:

Intel Nova Lake NPU6 Expected To Deliver 74 TOPS Of AI Performance

As per the claim by a prominent leaker, the Intel Nova Lake will boast NPU6 that will deliver up to 74 AI TOPS performance.

wccftech.com

NPU is going above 70 TOPS(INT 8) but 2 units of Xe3 iGPU is kinda a compromise, 4Xe3 would have been good but NPU gotta take space.

It seems NVL-S and -HX get 2Xe3(plus some other feature removal ?)
NVL-H with large iGPU : 12Xe3P tile
NVL-H with small iGPU : 4Xe3
NVL-U : 4Xe3
WCL : 2Xe3(minus the RT units ?)

NVL-H with 12Xe3P iGPU should be a really good all-round chip.

 

[Fjodor2001]

Top end NVL-S SKUs expected to get 288 MB bLLC (2x144 MB):

Intel Nova Lake-S CPU Lineup Include Four bLLC Models: 48 Core, 40 Core, 24 Core, 20 Core With 288 MB Dual & 144 MB Caches To Tackle Ryzen 3D V-Cache

Intel's Nova Lake-S Desktop CPUs will reportedly include at least four models with bLLC cache in dual and single compute tile flavors.

wccftech.com

Then there's also this note:

"These chips will come configured with 144 MB of bLLC across each compute tile for a total of 288 MB cache. That's in addition to the L2 and L3 cache offered per compute tile, so the final number is going to be massive"

So apparently Intel is specifying it differently than AMD. Because for e.g. 9950X3D, AMD specifies it as 144MB, but that's the total amount of cache (128 MB V-Cache + 16 MB L3).

I'm wondering why Intel decided on 144 MB bLLC (not including Lx caches) though. Isn't it normally a power of 2?

 

[511]

I'm wondering why Intel decided on 144 MB bLLC (not including Lx caches) though. Isn't it normally a power of 2?

Multiple of 2

 

[coercitiv]

Isn't it normally a power of 2?

At the lower level there's bound to be a building block sized to a power of 2, but the cache as a whole is more like a multiple of the number of cores within the chip. For example, in the case of ARL one needs to take into account the number of ring stops and multiply that by the the cache slice for each stop, which results in 36MB (12 stops x 3MB per slice).

Taking that into account, 144 is 12x12.

 

[Kepler_L2]

At the lower level there's bound to be a building block sized to a power of 2, but the cache as a whole is more like a multiple of the number of cores within the chip. For example, in the case of ARL one needs to take into account the number of ring stops and multiply that by the the cache slice for each stop, which results in 36MB (12 stops x 3MB per slice).

Taking that into account, 144 is 12x12.

It's 8 stops (one per 2x P-core, one per 4x E-core) with 4.5MB per slice for the regular variant and 18MB for bLLC.

 

[Fjodor2001]

Interesting that both chose 144 MB, but AMD decided to include Lx caches in that number but Intel didn’t. Or perhaps Intel also will include the Lx caches in the number when it’s actually released and marketed, so it goes above 144 MB per compute tile.

 

[Fjodor2001]

It's 8 stops (one per 2x P-core, one per 4x E-core) with 4.5MB per slice for the regular variant and 18MB for bLLC.

So for the non-bLLC variant of the NVL-S 8P+16E compute tile, there will be 8x4.5MB = 36 MB of what, e.g. L3 cache?

And does it mean the bLLC variant will have 36 MB (L3) + 144 MB (bLLC) = 180 MB in total per compute tile?

 

[João Bortolace]

So for the non-bLLC variant of the NVL-S 8P+16E compute tile, there will be 8x4.5MB = 36 MB of what, e.g. L3 cache?

And does it mean the bLLC variant will have 36 MB (L3) + 144 MB (bLLC) = 180 MB in total per compute tile?

bLLC is L3

 

[Fjodor2001]

bLLC is L3

Well as also quoted in the post above with the article it said:

"These chips will come configured with 144 MB of bLLC across each compute tile for a total of 288 MB cache. That's in addition to the L2 and L3 cache offered per compute tile, so the final number is going to be massive"

But maybe they got it wrong then?

 

[Kepler_L2]

Well as also quoted in the post above with the article it said:

"These chips will come configured with 144 MB of bLLC across each compute tile for a total of 288 MB cache. That's in addition to the L2 and L3 cache offered per compute tile, so the final number is going to be massive"

But maybe they got it wrong then?

It's not in addition, bLLC is just the large L3 version of Nova Lake

 

[511]

I am personally waiting forr MLID Tweet/Video confirming he was right all along.

 

[deasd]

Well, well.

It's not in addition, bLLC is just the large L3 version of Nova Lake

https://twitter.com/x/status/1993710093511340441

https://twitter.com/x/status/1993712138142290358

If this turns out to be HEDT Nova Lake, would be one of the greatest plot twist in speculation of past few generations of products.

 

[adroc_thurston]

If this turns out to be HEDT Nova Lake, would be one of the greatest plot twist in speculation of past few generations of products

NVL-WS is a separate platform.
NVL-S has max 1 bLLC tile, even for 2t configs.
Same rules as AMD.

 

[511]

There is no need for additional CCX/CCD Cache it will not be any fast than single CCD

 

[Saylick]

Well as also quoted in the post above with the article it said:

"These chips will come configured with 144 MB of bLLC across each compute tile for a total of 288 MB cache. That's in addition to the L2 and L3 cache offered per compute tile, so the final number is going to be massive"

But maybe they got it wrong then?

Hassan doesn’t know what he’s talking about. His job literally just entails doomscrolling through Xitter until a leaker drops something, he screenshots it, then he churns up a 3 paragraph article for clicks as fast as he can.

 

[adroc_thurston]

Hassan doesn’t know what he’s talking about. His job literally just entails doomscrolling through Xitter until a leaker drops something, he screenshots it, then he churns up a 3 paragraph article for clicks as fast as he can.

They also scroll this forum.
It's been funny

 

[Khato]

There is no need for additional CCX/CCD Cache it will not be any fast than single CCD

Quite true. But remember that this is Intel - just because there's no performance justification for doing it doesn't mean they aren't going to do it anyway. Especially since it'll let them market a bigger number.

 

[adroc_thurston]

Quite true. But remember that this is Intel - just because there's no performance justification for doing it doesn't mean they aren't going to do it anyway. Especially since it'll let them market a bigger number.

This is the new Intel that likes good margins where they can get 'em.

 

[Fjodor2001]

Hassan doesn’t know what he’s talking about. His job literally just entails doomscrolling through Xitter until a leaker drops something, he screenshots it, then he churns up a 3 paragraph article for clicks as fast as he can.

Yeah, I guess so. They're useful as a source for picking up leaks and whatever quickly though. But the info has to be questioned in order to try to find out what is accurate and not. I think the collective forum members here does a good job in doing that.

 

[Fjodor2001]

NVL-WS is a separate platform.
NVL-S has max 1 bLLC tile, even for 2t configs.
Same rules as AMD.

What rules are those?

And you mean there won't be any 2x144 MB = 288 MB bLLC for 2 compute tile NVL-S SKUs, and if so why?